An AP SoC for a unified architecture |
| |
Authors: | XuBang Shen CuiHua Zhao |
| |
Institution: | Xi’an Microelectronics Research Institute, Xi’an 710054, China |
| |
Abstract: | An instruction level parallel computing paradigm and a unified architecture for an array processor (AP) on a chip (SoC) are presented in this paper. Here “APU SoC” is short for “an AP SoC for the unified architecture”. The MISD/MIMD architecture for instruction level parallel computing is unified with the SIMD architecture for data level parallel computing. As a result, all the computing can be implemented on an APU SoC. The APU SoC offers the rationale of an array structure for development in current technology, yet simplicity for the hardware (chip) and software (program) parallel designs. Just as a single processor chip can replace many function module chips, the APU SoC can replace the single-core/multi-core/many-core CPU chip for TLP computing and the ASIC/ASSP/FPGA/RC device array chip for Operation Level Parallel computing. |
| |
Keywords: | MP SoC AP SoC TLP DLP OLP ILP |
本文献已被 SpringerLink 等数据库收录! |
| 点击此处可从《中国科学通报(英文版)》浏览原始摘要信息 |
| 点击此处可从《中国科学通报(英文版)》下载免费的PDF全文 |