双状态机在LDPC码译码实现中的应用

FSM（Finite State Machine，有限状态机）的核心功能是能描述一系列具有逻辑顺序的事件，并能有效管理各个事件执行的步骤，它是一种较为特殊的时序电路。本文分析了LDPC码译码器的主控程序的结构，结合有限状态机的设计思想，采用了两个状态机交替工作的机制，在FPGA上实现了译码器的主控模块，使初始信息存储模块、校验消息处理模块、变量消息处理模块、累加模块及校验模块有序工作，实现了模块间的无缝链接，使译码器工作稳定可靠。

Application of Double State Machine in LDPC Decoding Implementation

FSM(Finite State Machine)as a special timing circuit, The foremost function is that it can describe a series of event with consecution, make events works orderly. This paper analyzes the main control program of the LDPC decoder structure, Combined with the design of finite state machine, The two state machines to alternate work mechanism , The realization of the main control module in FPGA decoder, The initial information storage module, check the message processing module, variable message processing module, check module cumulative module and orderly work, To achieve a seamless link between modules, The decoder is stable and reliable in work.