基于FPGA的流水线珠算加法器设计

在图像处理、数字信号处理等领域需要用到大量加法运算，加法器运算性能对整个系统影响重大。根据操作模型原理，采用珠算算法设计了一个流水结构的并行高速硬件加法器，并在Xilinx Virtex-II的FPGA上实现了设计方案。在FPGA上集成8个处理单元完成并行计算，处理单元运用流水线结构，提高运算频率，并采用数据调度模块解决流水线上“数据相关”问题。仿真结果表明，32位珠算加法器平均运算仅需0.712ns，其速度是32位串行加法器的8.771倍，是32位并行加法器的1.588倍。这对于进一步优化实现硬件乘法器，甚至最终实现硬件除法器提供了研究空间。

Design of Pipeline Abacus Adder based on FPGA

As large quantities of addition is involved in the fields of image processing, digital signal processing and so forth, the performance of an adder possesses an important impact on the overall system. Based on the principles of operational model, a pipeline, parallel and high-speed hardware adder is designed adopting abacus algorithm, which is implemented on Xilinx Virtex-II FPGA. Eight processing units are integrated on FPGA to achieve parallel computation with pipeline structure applied in every processing unit to improve computing frequency, and the problem of data hazard in pipeline is solved with the data scheduling module. The simulation results indicate that the average computing cycle for a 32-bit abacus adder is only 0.712ns, faster than that of a 32-bit ripple carry adder by a factor of 8.771 and than that of 32-bit parallel adder by a factor of 1.588. This offers broad research space to further optimize hardware multiplier or even achieve hardware divider.