| 基于FPGA的同步动态随机存储器测试仪的实现 |
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| 引用本文： | 陈康,何明华.基于FPGA的同步动态随机存储器测试仪的实现[J].贵州大学学报(自然科学版),2009,26(6):91-95. |
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| 作者姓名： | 陈康 何明华 |
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| 作者单位： | 福州大学电气工程学院,福建,福州,350007 |
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| 摘 要： | 针对动态同步存储器在高速运行时出现的读写错误，设计了一种自动测试仪，允许自动改变电压，自动调整同步内存的参数，通过大量数据读写内存来确定故障芯片对哪种参数比较敏感，从而确定测试方案。
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| 关 键 词： | SDRAM FPGA VHDL 时序约束 工作电压 |
SDRAM Tester Design Based on FPGA |
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| CHEN Kang,HE Ming-hua.SDRAM Tester Design Based on FPGA[J].Journal of Guizhou University(Natural Science),2009,26(6):91-95. |
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| Authors: | CHEN Kang HE Ming-hua |
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| Institution: | ( Electrical Engineering School, Fuzhou University, Fuzhou350007, China) |
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| Abstract: | This article mainly discusses how to design SDRAM tester, which can read, write and compare the mass data, regulate the working voltage and the SDRAM parameter automatically, in order to know which parameter the failure chip is sensitive to. |
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| Keywords: | SDRAM FPGA VHDL |
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