| 高速图像处理嵌入式系统的设计 |
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| 引用本文： | 陈素华,郭利辉. 高速图像处理嵌入式系统的设计[J]. 许昌师专学报, 2011, 0(5): 64-67 |
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| 作者姓名： | 陈素华 郭利辉 |
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| 作者单位： | 许昌学院电气信息工程学院,河南许昌461000 |
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| 基金项目： | 基金项目：许昌学院教研项目（02009040） |
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| 摘 要： | 介绍了一种基于现场可编程逻辑阵列和数字信号处理器协同作业的高速图像处理嵌入式系统．设计了一种新颖的数据传输结构，该结构借助于单片双口RAM（将其内部等分两部分），利用乒乓技术完成对高速实时图像数据的缓冲．整个系统中所有工作，在FPGA和DSP间分工且形成流水，比使用单片DSP建立的处理系统性能提高25％左右．该系统具有可重构性，方便其它的算法于该系统上实现．
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| 关 键 词： | FPGA DSP 双口RAM 图像处理 |
Design of High-speed Image Processing Embedded System based on FPGA and DSP |
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| CHEN Su-hua,GUO Li-hui. Design of High-speed Image Processing Embedded System based on FPGA and DSP[J]. Journal of Xuchang Teachers College(Social Science Edition), 2011, 0(5): 64-67 |
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| Authors: | CHEN Su-hua GUO Li-hui |
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| Affiliation: | (College of Electrical and Information Engineering, Xuchang University, Xuchang 461000, China) |
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| Abstract: | A high-speed image processing embedded system based on the field programmable gate array and high-speed digital signal proeessor is designed in this paper. A novel data transmission structure with a dual-port RAM which is divided into two halves is applied to buff the high-speed real-time image data by means of Pingpong technique. Because all work in the system is divided between the FPGA and DSP in the form of the pipelined, it is 25% higher than the processing system based on the single DSP in performance. This system is easy to transplant other algorithms for its reconfigurability. |
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| Keywords: | FPGA DSP Dual-port RAM image compression |
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