| CMOS电路的低功耗逻辑综合 |
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| 引用本文： | 刘丹单,邬齐荣,马瑶,龚敏.CMOS电路的低功耗逻辑综合[J].四川大学学报(自然科学版),2007,44(1):106-110. |
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| 作者姓名： | 刘丹单 邬齐荣 马瑶 龚敏 |
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| 作者单位： | 四川大学物理科学与技术学院微电子技术四川省重点实验室,成都,610064 |
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| 摘 要： | 针对CMOS电路的功耗来源提出了一种低功耗综合流程.这种综合流程在不改变原有电路设计的前提下同时采用了门控时钟、操作数隔离和门级功率优化来降低功耗.对一个PTC(PWM/Timer/Counter)控制器的仿真表明，这种流程可以降低电路功耗57%，与仅使用门控时钟的流程相比可以进一步降低电路功耗21%.
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| 关 键 词： | 逻辑综合 低功耗 门控时钟 操作数隔离 门级功率优化 |
| 文章编号： | 0490-6756（2007）01-0106-05 |
| 修稿时间： | 2006-08-10 |
A logic synthesis flow of low power consumption CMOS circuit |
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| LIU Dan-dan,WU Qi-rong,MA Yao,GONG Min.A logic synthesis flow of low power consumption CMOS circuit[J].Journal of Sichuan University (Natural Science Edition),2007,44(1):106-110. |
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| Authors: | LIU Dan-dan WU Qi-rong MA Yao GONG Min |
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| Institution: | Sichuan Province Key laboratory of Microelectronics School of Physical Science and Technology, Sichuan University, Chengdu 610064, China |
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| Abstract: | A synthesis flow of low power consumption CMOS circuit has been introduced. This flow could use the gated clock, the operand isolation and the gate level optimization to decrease the power consumption without changing the original design. This technology has been used to design a PTC (PWM/Timer/Counter) controller, and the results indicated that 57% of the circuit power consumption has been reduced, while only 21% compared reduced if only the technology of gated clock was used. |
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| Keywords: | logic synthesis low power consumption gated clock operand isolation gate-level power optimization |
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