一种改进的用于FPGA快速部分配置的电路结构

设计了一种可以对现场可编程逻辑阵列(FPGA)内部编程点单元进行快速和局部配置的集成电路结构.主要特点是:在采用指令集方式的32位数据总线结构上增设局部配置控制寄存器和地址译码逻辑,可以实现FPGA的快速局部配置;针对Xilinx Virtex系列FPGA中存在的"内存一致性"问题,提出了有效的解决方案.与Xilinx Virtex器件只能以帧为单位对内部编程点进行配置相比,该结构可以对FPGA内部任意一个编程点进行单独配置,具有更强的灵活性.

An Improved Circuit Architecture for Fast and Partial Configuration of FPGA

An improved architecture for fast and partial configuration of FPGA is proposed.A 32 bits wide data bus,controlled by an instruction set is adopted.A partial control register and address decoding logic are added to the architecture.An effective solution is proposed to solve the memory coherence problem of Virtex Series FPGA.Compared with the configuration architecture of Virtex Series FPGA,which can only configure memory cells by frame,the proposed new architecture is more flexible.It can configure any single memory cell in FPGA.