| CRC Look-up Table Optimization for Single-Bit Error Correction |
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| 作者姓名： | 潘赟 葛宁 董在望 |
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| 作者单位： | Department of Electronic Engineering, Tsinghua University, Beijing 100084, China |
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| 摘 要： | Many communication systems use the cyclic redundancy code （CRC） technique for protecting key data fields from transmission errors by enabling both single-bit error correction and multi-bit error detection. The look-up table design is very important for the error-correction implementation. This paper presents a CRC look-up table optimization method for single-bit error correction. The optimization method minimizes the address length of the pre-designed look-up table while satisfying certain restrictions. The circuit implementation is also presented to show the feasibility of the method in the application specific integrated circuit design. An application of the optimization method in the generic framing procedure protocol is implemented using field programmable gatearrays. The result shows that the memory address length has been minimized, while keeping a very simple circuit implementation.
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| 关 键 词： | 循环冗余编码 查表最优化 比特误差 纠错 |
| 收稿时间： | 13 May 2006 |
| 修稿时间： | 2006-05-13 |
CRC Look-up Table Optimization for Single-Bit Error Correction |
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| PAN Yun,GE Ning,DONG Zaiwang.CRC Look-up Table Optimization for Single-Bit Error Correction[J].Tsinghua Science and Technology,2007,12(5):620-623. |
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| Authors: | PAN Yun GE Ning DONG Zaiwang |
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| Institution: | Department of Electronic Engineering, Tsinghua University, Beijing 100084, China |
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| Abstract: | Many communication systems use the cyclic redundancy code (CRC) technique for protecting key data fields from transmission errors by enabling both single-bit error correction and multi-bit error detection. The look-up table design is very important for the error-correction implementation. This paper presents a CRC look-up table optimization method for single-bit error correction. The optimization method minimizes the address length of the pre-designed look-up table while satisfying certain restrictions. The circuit implementation is also presented to show the feasibility of the method in the application specific integrated circuit design. An application of the optimization method in the generic framing procedure protocol is implemented using field programmable gate arrays. The result shows that the memory address length has been minimized, while keeping a very simple circuit implementation. |
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| Keywords: | cyclic redundancy code look-up table optimization single-bit error correction generic framing procedure |
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