基于FPGA的软件滤波算法设计及实现

在实际电路的设计过程中,经常会涉及到FPGA的使用。而外界的干扰脉冲或毛刺信号会影响其稳定性,为了避免电路做出错误的动作,需要对输入信号进行滤波处理。详细讲述了延时滤波和判决滤波两种基于VHDL语言的软件滤波方法,并通过实验证明了两种滤波方法均能有效消除干扰信号,验证了其可靠性。

Design and Implementation of Software Filtering Algorithm Based on FPGA

The use of a FPGA is often involved in the actual circuit design process. But outside interference pulse or burr signal can influence its stability. In order to avoid that the circuit makes the wrong action at this point, we need to filter the input signal. Two kinds of filter methods based on VHDL language are described in details in this paper, they are time delay filtering and judgment filtering. Experiments have shown that both the two methods can effectively eliminate the interference signal. Their reliability have been verified.