基于状态空间的FPGA功能仿真策略

随着FPGA(field programmable gate array)芯片集成度的提高,基于FPGA的复杂系统设计成为数字电路的发展趋势,如何实现复杂电路的功能仿真成为设计者面临的难题。针对不同规模的FPGA设计,划分输入状态空间,提出了遍历性激励与伪随机激励相结合、软硬件协同的功能仿真策略,完成了4位半加器和32位乘法器的功能仿真实例。测试结果表明新的功能仿真策略能够加快仿真速度,尤其是对大规模FPGA设计。

Function simulation strategy based on state space of FPGA

With the increasing integration of field programmable gate array(FPGA) chips, complex system designs based on FPGA become the development trend in digital circuit,so how to simulate the function of complex circuits is a challenge to designers. In this paper,by dividing inputs state space, a function simulation strategy is presented. The new strategy combines ergodic test stimuli with pseudo-random test stimuli and collaborates software and hardware for different FPGA design scale. The paper accomplishes the function simulation of 4bits half adder and 32 bits multiplier. Experimental results indicate that the new function simulation strategy can speed up simulation, especially for large-scale FPGA design.