基于现场可编程门阵列的矩阵求逆算法设计

针对自适应抗干扰算法在更新最优权值时存在时间延迟问题,提出了一种基于Cholesky分解的矩阵求逆算法实现架构。该实现架构主要包括协方差矩阵计算模块、Cholesky分解模块、计算下三角矩阵的逆矩阵模块、三角矩阵相乘和权值计算模块。本设计可完成在最短权值更新时间的前提下,对高阶采样矩阵进行求逆运算。仿真结果表明,在FPGA的硬件平台上,一次权值的更新时间只需要1.2 ms。本设计为自适应抗干扰快速求解权值提供了一种切实可行的解决方案,对存在类似需求的权值求解系统具有一定的参考价值。

Design of Implementation Architecture for Fast Sampling Matrix Inversion Algorithm Based on FPGA

A matrix inversion algorithm implementation architecture based on Cholesky decomposition is proposed to address the time delay issue of adaptive anti-interference algorithms in updating optimal weights. The implementation architecture mainly includes a covariance matrix calculation module, a Cholesky decomposition module, an inverse matrix module for calculating the lower triangular matrix, a triangular matrix multiplication and weight calculation module. This design can perform inverse operations on high-order sampling matrices with the shortest weight update time. The simulation results show that on the hardware platform of FPGA, the update time of a weight value only needs 1.2ms. This design provides a practical and feasible solution for adaptive anti-interference to quickly solve weight values, and has certain reference value for weight solving systems with similar requirements.