| 高速带通型△∑AD转换电路设计 |
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| 引用本文： | 林海军.高速带通型△∑AD转换电路设计[J].厦门理工学院学报,2013(2):56-60. |
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| 作者姓名： | 林海军 |
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| 作者单位： | 厦门理工学院光电与通信工程学院,福建厦门361024 |
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| 基金项目： | 厦门理工学院高层次引进人才科技项目（YKJ12003R） |
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| 摘 要： | 采用欠采样技术和低功耗Gm-C带通振荡电路技术,实现了一种4阶连续时间高速带通型△∑AD转换电路的低功耗化设计.通过TSMC 180 nm CMOS工艺的SPICE仿真,在信号中心频率2.4 GHz、工作带宽2 MHz、采样频率3.2 GHz条件下,实现了信噪失真比（SNDR）为50 dB,电源电压1.8 V时核心电路功耗为50 mW.
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| 关 键 词： | △∑AD转换电路 欠采样 低功耗 振荡电路 |
Design of High Speed Bandpass Delta-Sigma AD Modulator |
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| LIN Hai-jun.Design of High Speed Bandpass Delta-Sigma AD Modulator[J].Journal of Xiamen University of Technology,2013(2):56-60. |
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| Authors: | LIN Hai-jun |
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| Institution: | LIN Hai-jun ( School of Optoelectronic ＆ Communication Engineering, Xiamen University of Technology, Xiamen 361024, China) |
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| Abstract: | This paper presents the design of a 4th order continuous time bandpass delta-sigma AD modulator with low paper by use of sub-sampling technique and a very low power Gm-C bandpass resonator. By TSMC O. 18 um CMOS process, when the SPICE simulation results express the center frequency of input signal is 2. 4 GHz, the sampling frequency is 3.2 GHz, and signal band is 2 MHz, 50 dB of SNDR （ Signal to Noise ＋ Distortion Ratio） is obtained, and the power consumption from a 1.8 V voltage supply is 50 mW. |
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| Keywords: | delta-sigma ad modulator sub-sampling low power oscillator |
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