基于DVB-S2的高速多码率LDPC编码器的FPGA设计与实现

针对DVB-S2标准中的低密度奇偶校验(LDPC)码,提出了一种LDPC编码器设计结构. 该结构巧妙地利用了输入数据的随机特性,显著降低了计算电路的功耗. 在此基础上,提出了两路并行的编码器设计方法,将编码器可处理的信息速率提高到原来的2倍. 在现场可编程门阵列(FPGA) XC4VLX25-10SF363上实现了两路并行的多码率LDPC编码器. 经实验测试表明,编码器工作稳定,处理速率高达328Mbit/s,可满足同步数字传输体系(SDH)高速传输的应用需求,同时,该编码器具有通用性,经过重新配置可实现具有类似校验矩阵的LDPC编码.

FPGA Design and Implementation of High Speed Multi-Rate LDPC Encoder Based on DVB-S2

An encoder architecture of low density parity check(LDPC) code defined in DVB-S2 standard is proposed.The power dissipation of the computation circuit is reduced obviously through the smart exploitation of the random characteristic of the input data sequence.Furthermore,a design scheme of LDPC encoder with two parallel inputs is presented,which doubles the processing information rate.The multi-rate LDPC encoder with two parallel inputs was implemented on the field programmable gate array(FPGA) XC4VLX25-10SF363,and was tested under the experimental system.The tested results showed that the encoder could work normally with the processing rate up to 328Mbit/s,which could satisfy the requirements of high speed synchronous digital hierarchy(SDH) transmission application.Additionally,this encoder is flexible to implement encoding of LDPC code with similar parity check matrices via reconfiguration.