| UHF波段PLL频率合成器的设计 |
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| 引用本文： | 王利众. UHF波段PLL频率合成器的设计[J]. 太原师范学院学报(自然科学版), 2011, 10(4) |
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| 作者姓名： | 王利众 |
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| 作者单位： | 中央民族大学信息工程学院,北京,100081 |
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| 基金项目： | 中央民族大学2008年度青年教师科研基金项目(08QNA31) |
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| 摘 要： | 介绍了锁相环频率合成技术的基本原理、特点及应用,并给出了一个以TDD1742T为核心芯片的UHF波段（900MHz）PLL频率合成器的设计方案.
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| 关 键 词： | 频率合成器 锁相环 环路滤波器 压控振荡器 |
The Design of a UHF Band PLL Frequency Synthesizer |
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| Wang Lizhong. The Design of a UHF Band PLL Frequency Synthesizer[J]. Journal of Taiyuan Normal University:Natural Science Edition, 2011, 10(4) |
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| Authors: | Wang Lizhong |
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| Affiliation: | Wang Lizhong(Department of Information Engineering,Minzu University of China,Beijing 100081,China) |
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| Abstract: | The fundamentals,features and applications of phase-locked loop frequency synthesis technology are presented,and a design scheme of a UHF band(900 MHz) PLL frequency synthesizer using TDD1742T as the core IC chip is also given. |
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| Keywords: | frequency synthesizer phase-locked loop loop filter voltage-controlled oscillator |
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