| A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse |
| |
| 引用本文： | ZHANG Tao ZOU Xuecheng ZHAO Guangzhou SHEN Xubang. A PLL Clock Frequency Multiplier Using Dynamic Current Matching Adaptive Charge-Pump and VCO Frequency Reuse[J]. 武汉大学学报:自然科学英文版, 2007, 12(3): 491-495. DOI: 10.1007/s11859-006-0072-7 |
| |
| 作者姓名： | ZHANG Tao ZOU Xuecheng ZHAO Guangzhou SHEN Xubang |
| |
| 作者单位： | [1]College of Information Science and Engineering, Wuhan University of Science and Technology, Wuhan 430070, Hubei, China [2]Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan 430074, Hubei, China [3]Institute of Pattern Recognition and Artifical Intelligence, Huazhong University of Science and Technology, Wuhan 430074, Hubei, China [4]Xi＇an Microelectronic Technology Institute, Xi＇an 710054, Shaanxi, China |
| |
| 基金项目： | Supported by the National Key Pre-Research Project of China （413010701-3） |
| |
| 摘 要： | A 3.5 times PLL clock frequency multiplier for low voltage different signal （LVDS） driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator （VCO） is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor （CMOS） process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time .
|
| 关 键 词： | 锁相回路 低电压差分信号 乘法器 VCO频率复用 |
| 文章编号： | 1007-1202（2007）03-0491-05 |
| 收稿时间： | 2006-07-03 |
| 修稿时间： | 2006-07-03 |
A PLL clock frequency multiplier using dynamic current matching adaptive charge-pump and VCO frequency reuse |
| |
| Zhang Tao,Zou Xuecheng,Zhao Guangzhou,Shen Xubang. A PLL clock frequency multiplier using dynamic current matching adaptive charge-pump and VCO frequency reuse[J]. Wuhan University Journal of Natural Sciences, 2007, 12(3): 491-495. DOI: 10.1007/s11859-006-0072-7 |
| |
| Authors: | Zhang Tao Zou Xuecheng Zhao Guangzhou Shen Xubang |
| |
| Affiliation: | (1) College of Information Science and Engineering, Wuhan University of Science and Technology, Wuhan, 430070, Hubei, China;(2) Department of Electronic Science and Technology, Huazhong University of Science and Technology, Wuhan, 430074, Hubei, China;(3) Institute of Pattern Recognition and Artifical Intelligence, Huazhong University of Science and Technology, Wuhan, 430074, Hubei, China;(4) Xi’an Microelectronic Technology Institute, Xi’an, 710054, Shaanxi, China |
| |
| Abstract: | A 3.5 times PLL clock frequency multiplier for low voltage different signal (LVDS) driver is presented. A novel adaptive charge pump can automatically switch the loop bandwidth and a voltage-controlled oscillator (VCO) is designed with the aid of frequency ranges reuse technology. The circuit is implemented using 1st Silicon 0.25 μm mixed-signal complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the PLL clock frequency multiplier has very low phase noise and very short capture time. Biography: ZHANG Tao (1967–), male, Associate professor, research direction: signal processing and digital/analog mixed integrated circuits design. |
| |
| Keywords: | low voltage different signal phase locked loop multiplier adaptive charge pump phase noise |
| 本文献已被 CNKI 维普 SpringerLink 等数据库收录！ |
|
