| H.264/AVC编码器中6阶插值滤波器的实现 |
| |
| 作者单位： | 北京大学深圳研究生院集成微系统重点实验室，北京大学软件与微电子学院，安康学院物理与计算机系 |
| |
| 摘 要： | 针对H.264/AVC视频编码器的系统芯片设计,提出了6阶1/2像素插值滤波器的4种具体实现结构;并且在相同的约束条件下,使用Synopsys综合工具比较了各自的实现代价,最终给出了6阶1/2像素插值滤波器的优化实现结构。
|
| 关 键 词： | H.264/AVC视频编码器 6阶插值滤波器 芯片面积 路径延迟 |
Realization of 6-Tap Finite Impulse Response Interpolation Filter for H.264/AVC Encoder |
| |
| Authors: | WANG Qingchun CAO Xixin LU Weijun HE Xiaoyan CAO Jian |
| |
| Institution: | WANG Qingchun~ 1) CAO Xixin~ 2) LU Weijun~ 2) HE Xiaoyan~ 3) CAO Jian~ 2) |
| |
| Abstract: | It is proposed that four hardware architectures of 6-tap finite impulse response interpolation filter for the design of H.264/AVC encoder (SOC). Moreover, based on comparative analysis of Synopsys Design Compiler to implement the hardware at the same constraint, an efficient half pixel interpolation filter (6-tap FIR) architecture had been given finally. |
| |
| Keywords: | H 264/AVC video encoder 6-tap finite impulse response interpolation filter chip area delay |
| 本文献已被 CNKI 等数据库收录！ |
