基于归并算法的高速LDPC流水线译码器设计与实现

LDPC码是一种纠错能力极强的编码,已广泛用于新一代数字电视,深空探测,卫星通讯等多种领域,基于不同要求出现了许多不同的编码标准,所以定制化的LDPC码译码算法的硬件实现已成为当今的研究热点之一。为满足卫星通信中高速数据传输的需求,使用LDPC码Normalized最小和译码硬件实现算法以及归并算法原理,并结合FPGA适合并行计算的特点,提出一种基于流水线的部分并行LDPC译码的FPGA设计,通过仿真和实验,最终完成满足卫星高速通信需求的LDPC译码器设计。最终使用Altera公司FPGA上完成译码器设计,整个系统在时钟频率为150 MHz的条件下,数据处理速率达到1.5Gb/s以上,数据吞吐率达到750 Mb/s纠错性能优异,完全满足卫星高速数据处理要求。

Design and Implementation of a High-speed Pipelined LDPC DecoderBased on Merging algorithm

LDPC is an error correction code with excellent performance and simple decoder structure, which is widely used in deep space exploration, satellite communications and many other fields. To meet the demand for satellite communications in high-speed data transmission, this paper presents a kind of the pipeline parallel LDPC FPGA decoder based on Normalized minimum sum decoding algorithm and merge algorithm principle. A high-speed LDPC decoder is designed to meet the CCSDS standard based on FPGA pipeline architecture. Finally LDPC decoder is designed with the Altera FPGA, and its data processing rate is over 1.5 Gbps , and the data throughput process at speeds up to 750Mbps, when the work clock frequency is 150MHz. with its excellent error correction performance, it is fully meet the high-speed data processing requirements.