时钟数字平滑技术在FPGA中的设计

时钟平滑技术是复分接系统中关键的接口技术，传统设计中锁相环部分使用FPGA外围芯片电路实现。占用硬件空间，成本高，又由于是模拟电路而调试复杂。该文提出了一种不使用任何外围电路而用FPGA内部逻辑实现对基群信号非均匀数据和时钟的平滑处理技术，并例举实例，论述设计中的参数设置和时钟切换技巧。

Technology of Clock Digital Flatness in FPGA

The technology of clock flatness has been one of the essential interface techniques in multiplex system. On traditional design there should be a set of analogue circuits, coursing a lot of hardware and complex debugging. This paper introduces the technology by using FPGA to implement the Primary order signals, Clock Digital Flatness, especially with the illustration of parameter setting and clock - switching.