| A High Speed Signal Processing Machine -Its Architecture, Language and Compiler |
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| 引用本文： | Wang Yufei and Yu ShiqiBeijing Institute of Data Processing Technology,P.O.Box 3927,Beijing 100039,China. A High Speed Signal Processing Machine -Its Architecture, Language and Compiler[J]. 系统工程与电子技术(英文版), 1991, 0(1) |
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| 作者姓名： | Wang Yufei and Yu ShiqiBeijing Institute of Data Processing Technology P.O.Box 3927 Beijing 100039 China |
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| 作者单位： | Wang Yufei and Yu ShiqiBeijing Institute of Data Processing Technology，P.O.Box 3927，Beijing 100039，China |
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| 摘 要： | A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.
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A High Speed Signal Processing Machine -Its Architecture, Language and Compiler |
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| Wang Yufei and Yu ShiqiBeijing Institute of Data Processing Technology,P.O.Box ,Beijing ,China. A High Speed Signal Processing Machine -Its Architecture, Language and Compiler[J]. Journal of Systems Engineering and Electronics, 1991, 0(1) |
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| Authors: | Wang Yufei Yu ShiqiBeijing Institute of Data Processing Technology P.O.Box Beijing China |
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| Affiliation: | Wang Yufei and Yu ShiqiBeijing Institute of Data Processing Technology,P.O.Box 3927,Beijing 100039,China |
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| Abstract: | A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler. |
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| Keywords: | Parallel processing Systolic array processor Parallel language Compiler. |
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