一种提高流水线模数转换器速度的方法

针对电荷转移流水线模数转换器 (ADC)的结构特点 ,提出了一种增加模数转换速度而保持功耗不变的方法。该方法在流水线级电路的采样相引入一个额外的时钟相来释放要接入到前级反馈放大器的电容上的电荷 ,以此来优化反馈放大器建立过程的起点 ,从而减小最大可能的建立时间。理论分析和计算机仿真表明 :该方法对常用的电荷转移流水线结构均有效 ,但更适用于低级分辨率、低线性输入范围、低建立精度和低电容缩减系数的流水线结构。当在低线性输入范围、无电容缩减处理的 1b/级或 1.5 b/级的流水线结构中应用该方法时 ,可将 A/ D转换周期降低达 30 %。

Novel method for improving the speed of pipelined A/D converters

A new method is presented for reducing the settling time of a feedback amplifier in a charge transferred pipelined A/D converter to improve the A/D conversion speed. An extra clock phase is introduced in the sampling phase of the pipelined stage to release the charge on the capacitors which are going to be connected to the upper stage amplifier output. The initial step of the settling response is then optimized which reduces the maximum settling time. The proposed method is proved useful for commonly used pipelined architectures, especially for those with low stage resolution, small op amp linear input ranges, low settling precision requirements, and small capacitor scaling factors. The conversion period can be reduced by more than 30% with this method in a 1 bit per stage or 1.5 bit per stage architecture with a small op amp linear input range and no capacitor scaling.