| 一种H.264／AVC解码器关键技术的设计 |
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| 引用本文： | 谭立地,林浩,徐昕,周娅.一种H.264／AVC解码器关键技术的设计[J].江西科学,2008,26(4). |
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| 作者姓名： | 谭立地 林浩 徐昕 周娅 |
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| 作者单位： | 1. 江西省科学院,江西,南昌330029
2. 华中科技大学,湖北,武汉,430074 |
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| 摘 要： | 本文提出了H.264/AVC解码器的系统结构及其核心单元总体结构的设计研究方案.重点包括系统的流水线设计、双总线设计以及IDCT变换、帧内预测、帧间运动补偿等关键模块的设计与大规模逻辑实现.硬件解码部分在200 MHz 系统时钟时可以实时解码H.264 High 4:4:4 profile 4.0 level码流.
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| 关 键 词： | 解码器 关键技术 |
Design of the key Technology in H.264/AVC Decoder |
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| TAN Li-di,LIN Hao,XU Xin,ZHOU Ya.Design of the key Technology in H.264/AVC Decoder[J].Jiangxi Science,2008,26(4). |
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| Authors: | TAN Li-di LIN Hao XU Xin ZHOU Ya |
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| Abstract: | This paper proposed the architecture of the H.264/AVC decoding system and shared the design research plan of its core unit.The research covered the design of some key modules and its large-scale logical implementation.The covered topics are:the overall system pipeline design,the dual-bus design,the IDCT transformation,the inter prediction,and the frame motion compensation.The hardware decoder can decode one bit stream,complied with H.264 specification High 4:4:4 profile 4.0 level bit stream,in real time running a system clock at 200 MHz. |
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| Keywords: | H 264/AVC VLSI/ASIC/SoC |
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