| A Novel Testability-Oriented Data Path Scheduling Scheme in High-Level Synthesis |
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| 作者单位： | Department of Automation Tsinghua University，Department of Automation，Tsinghua University，Department of Automation，Tsinghua University，Department of Automation，Tsinghua University，Department of Automation，Tsinghua University，Beijing 100084，China，Beijing 100084，China，Beijing 100084，China，Beijing 100084，China，Beijing 100084，China |
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| 基金项目： | 国家重点基础研究发展计划(973计划);国家自然科学基金 |
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| 摘 要： | Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay.
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A Novel Testability-Oriented Data Path Scheduling Scheme in High-Level Synthesis |
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| CHENG Benmao,WANG Hong,YANG Shiyuan,NIU Daoheng,JIN Yang. A Novel Testability-Oriented Data Path Scheduling Scheme in High-Level Synthesis[J]. Tsinghua Science and Technology, 2007, 12(Z1): 134-138 |
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| Authors: | CHENG Benmao WANG Hong YANG Shiyuan NIU Daoheng JIN Yang |
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| Abstract: | Scheduling is an important step in high-level synthesis and can greatly influence the testability of the synthesized circuits. This paper presents an efficient testability-improved data path scheduling scheme based on mobility scheduling, in which the scheduling begins from the operation with least mobility. In our data path scheduling scheme, the lifetimes of the I/O variables are made as short as possible to enlarge the possibility of the intermediate variables being allocated to the I/O registers. In this way, the controllability/observability of the intermediate variables can be improved. Combined with a weighted graph-based register allocation method, this scheme can obtain better testability. Experimental results on some benchmarks and example circuits show that the proposed scheme can get higher fault coverage compared with other scheduling schemes at little area overhead and even less time delay. |
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| Keywords: | high-level synthesis(HLS) scheduling testability mobility |
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