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可编程顶点处理器FPGA验证平台的设计与实现
引用本文:杨毅,郭立,史鸿声.可编程顶点处理器FPGA验证平台的设计与实现[J].中国科学技术大学学报,2009,39(11).
作者姓名:杨毅  郭立  史鸿声
作者单位:中国科学技术大学电子科学与技术系,安徽,合肥,230026
基金项目:教育部高等学校博士学科点专项基金 
摘    要:为了对一个面向移动设备的可编程顶点处理器进行功能验证和性能评估,设计了一个基于片上可编程系统(system on programmable chip,SoPC)的FPGA验证平台.在该平台上,采用软硬件协同验证的方法,成功地运行了多个顶点处理器程序.实验结果表明,该平台可以有效地验证可编程顶点处理器的功能,而且适用于3D图形处理器中其他模块的FPGA验证.

关 键 词:FPGA验证  可编程顶点处理器  软硬件协同验证

Design and implementation of FPGA verification platform for a programmable vertex processing unit
YANG Yi,GUO Li,SHI Hong-sheng.Design and implementation of FPGA verification platform for a programmable vertex processing unit[J].Journal of University of Science and Technology of China,2009,39(11).
Authors:YANG Yi  GUO Li  SHI Hong-sheng
Abstract:To process the functional verification and performance evaluation for a programmable vertex processing unit which was designed for mobile devices,a SoPC-based FPGA verification platform was proposed.A number of vertex processing unit programs on the platform had been run using software/hardware co-verification methods.The experimental results show that the verification platform can effectively verify the functions of the vertex processing unit and is suitable for verifying the other modules of the 3D graphics accelerator.
Keywords:SoPC  FPGA verification  programmable vertex processing unit  SoPC  software/hardware co-verification
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