| 利用微电子测试图形研究CMOS IC的锁定效应 |
| |
| 引用本文： | 林英 贺德洪. 利用微电子测试图形研究CMOS IC的锁定效应[J]. 华东师范大学学报(自然科学版), 1993, 0(3): 44-53 |
| |
| 作者姓名： | 林英 贺德洪 |
| |
| 作者单位： | 电子科学技术系，电子科学技术系，电子科学技术系 上海第二工业大学可靠性研究室工作 |
| |
| 摘 要： | 体硅CMOS IC内不可避免地存在着寄生pnpn四层结构,在一定条件下,导致器件闭锁失效.本文结合专门用于研究CMOSIC内锁定的微电子测试图形,对以设计、工艺制备的一系列组合测试结构,进行测试,并对锁定现象作对比分析,提出了优化设计的途径.
|
| 关 键 词： | 微电子 测试结构 CMOS IC 锁定 |
Study on the Latch-up Effect of CMOS IC by Using Microelectronic Test Patterns |
| |
| LIN YING, HE DEHONG, GUI LIMIN. Study on the Latch-up Effect of CMOS IC by Using Microelectronic Test Patterns[J]. Journal of East China Normal University(Natural Science), 1993, 0(3): 44-53 |
| |
| Authors: | LIN YING HE DEHONG GUI LIMIN |
| |
| Affiliation: | Department of Electronic Science & Technology |
| |
| Abstract: | The parasitic pnpn structure exists inherently in bulk CMOS IC.It leads devices to Latch-up failures under certain conditions.This paper studies Latch-up behavior comparatively through a series of tests on a set of composite-test Structures which have been designed and technologically manufactured.Then the approaches to optimum design are proposed. |
| |
| Keywords: | microelectronic test structure CMOS IC latch-up parasitic pnpn structure |
| 本文献已被 CNKI 维普 等数据库收录！ |
