High-speed parallel matched filter designing and FPGA implementation |
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| Authors: | Qinglin Zhang Shuzhen Chen Yijun Luo Shan Wang |
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| Institution: | (1) Texas Instruments Inc., Dallas, TX 75243, USA;(2) San Francisco State University, San Francisco, CA 94132, USA;(3) National Cheng Kung University, Tainan, Taiwan;(4) School of Electrical Engineering, Korea University, Anam-dong, Seongbuk-Gu, Seoul, 136-701, Korea;(5) Samsung Electronics Co., Hwasung, Korea;(6) School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907, USA |
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| Abstract: | Matched filter is one of the key technologies to achieve high-speed data transmission. In this paper, a parallel finite-impulse
response (FIR) filter structure based on polyphase filtering is used to achieve high-speed matched filter in quadrature phase-shift
keying (QPSK) demodulation up to 800 Mb · s−1. First, a window function is employed of to obtain impulse response of matched filter. Second, the high-speed parallel FIR
structure is presented based on polyphase filtering. Then, the filter with EP2S180F1020 on the Quartus II 7.2 platform is
achieved. The final results show that the design is correct and can implement high-speed matched filtering, wherein the equivalent
frequency of which is up to 2 037 MHz. In addition, this scheme is easy to realize, which brings great value to the application
of this filter in high-speed matched filters design in demodulation systems. |
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| Keywords: | parallel matched filter finite-impulse response (FIR) window function polyphase filtering field programmable gate array |
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