一种全数字延时触发器设计

传统的单稳延时电路需外接RC支路,故精度不高,稳定性差,预置不直观。与之相比,全数字化设计的触发器采用时钟计数与预设值较容易实现延时,准确性、稳定性大大提高。延时范围与时钟频率有关,亦随计数器位数增加而增加,最高分辨率由器件响应速度确定,定时精度与时钟步长有关。由于采用数字比较方法,可实现不同量程（μs~数10s）切换。该设计可用于要求较高的实验场合。

Design of Full Digital Time-lapse Trigger

The traditional monostable time delay circuit has to be connected to an exterior RC, resulting in bad accuracy and instability. Compared to this, the trigger with fully digitalized design has greatly improved the accuracy and stability because it realizes the time delay by comparing clock count with the prearranged value. The range of time delay is related to the frequency of clock and the number of counter digits. The devices speed determines the differentiability. The precision is related to the period of the input clock. Due to digitalized comparison methods, different ranges（ us - 10 s） can be realized. This design can be used in higher-demanding experiment.