基于流水线的复数阵列加法器的设计与实现

复数加法运算复杂,用硬件实现复数加法,需要使用数目众多的加法器,占用大量的面积。通过分析复数加法的运算过程,将计算过程流水化,对各加法器进行有效的复用,设计了一个阵列加法器的电路结构实现其功能,并将其用Verilog硬件设计语言描述后,在Modelsim6.0中完成了功能验证,在SyplifyPro7.0中完成了电路综合,并采用ISE7.1完成了布局布线。功能验证、电路综合及布局布线的结果表明设计正确,实现了复数加法运算,时序性能好,耗用资源少。

Design and Implementation for a Plurality Array Adder Based on Pipe-line Technique

Operation of plurality add is very complicated. In the design will numerous adders be used and large area will be consumed. Analyzing process of plurality operation, Pipeline technique is adoptd to reuse effectively the adder and designs circuit structure of array adder to implement the function. Using VefilogHDL, simulator in Modelsim Se 6. 0, synthesis in Synplify Pro 7.0 and fitter are carried out in ISE 7.1 successfully. The result of experiment shows that this design has good timing performance and few occupation of resource.