一种基于时延和功耗双重优化目标的布局算法

针对标准单元模式的超大规模集成电路布局问题,提出一种新的基于时延和功耗双重优化目标的布局算法.在以优化时延为目标函数的布局结果基础上,进一步降低芯片的功耗特性,并通过算法设计较好地解决了两者优化方向的一致性.通过标准单元测试电路的实验结果表明,该算法在时延及功耗优化方面综合性能良好.

A New Placement Algorithm Based on Timing-Driven and Power-minimized Optimization Objective

Facing the severe challenges of placement in very large scale integrated circuits based on standard cell,a new placement algorithm based on both timing-driven and power minimized optimization objective was presented.Based on the placement result which was optimized by timing-driven objective,the power dissipation of the circuit was minimized,Besides,this optimization method was well adopted to combine the timing-driven optimization and power minimization.According to the experimental results of MCNC(microelectronics centre of north -Carolina) standard cell benchmarks,the longest path delay and power dissipation are both improved.