ASIC仿真加速系统编译优化策略研究

随着微处理器设计技术的发展，基于硬件仿真加速器的系统验证已成为业内公认的最有效的系统验证方法,而系统仿真频率是硬件仿真加速器验证系统最重要的性能指标之一．本文以某款国产高性能通用微处理器FT-xx在ASIC仿真加速平台上的系统仿真加速为工程背景，通过调整编译选项、分析编译结果展开研究．首先分析了ASIC硬件仿真加速的加速原理，然后重点研究了逻辑资源数量、通用寄存器类型设计映射方式、特殊寄存器类型设计映射方式对系统仿真频率的影响．研究结果表明，当待验证设计的规模一定时，ASIC仿真器的逻辑资源并非越多越好、memorysize值的选取存在一个较佳范围、对于某些特殊的寄存器采用强制映射能极大地提高系统仿真频率．

An Effective Memory System Verification Method Based on ASIC Emulation Acceleration System

With the development of microprocessor, emulation accelerator based verification has become the most effective system verification method. And the system frequency is one of the most important indexes of the emulation acceleration system. Based on the engineering application of the system verification to a homemade high performance microprocessor FT-X on a ASIC emulator, research was done by tuning the compile parameters assisted with compile results analysis. The acceleration mechanism of ASIC accelerator was analyzed. And then, the effect of domain number, normal register design mapping method, special register design mapping method on the system emulation frequency was studied. The results show that it's not a good idea to increase the domain number as much as possible, because there exists a sound range of memory size when the design under test is fixed. And the system emulation frequency was increased sharply by the application of forcible mapping method to some special blocks on the other hand.