深亚微米和3D背景Cache延迟设计与模拟关键技术

研究了深亚微米和3D条件下的cache访问延迟的设计和模拟技术.对不同容量、不同关联度、不同技术的cache进行了模拟.实验结果显示，深亚微米条件下，互联网络成为影响cache访问延迟的重要因素，40 nm工艺下它可占cache总访问延迟的61.1%；tag比较器的延迟对cache访问延迟的影响可达9.5%.但后者并未得到已有模型的重视.鉴于此，对已有的cache访问延迟模型进行了改进.基于3D条件下多核处理器最后一级大容量cache(L3C)的容量不断增长的趋势，eDRAM在功耗和面积上的优势使其更具吸引力.模拟结果显示，在容量为1 MB, 4 MB及大于16 MB的L3C设计下，相同容量的eDRAM cache延迟比SRAM cache小，差值为8.1%(1 MB)至53.5%(512 MB).实验结果显示,未来3D多核处理器设计中eDRAM是设计L3C的更佳选择.

Key Techniques of Design and Simulation of Cache Access Time in Deep Sub-micron and 3-Dimension Era

This paper studied the key techniques of designing and simulating cache access time in deep sub-micron and 3-dimension era, and simulated the cache with different capacity, associativity and storage technology. The results show that, in 40nm technology, the interconnect network is a main source of the access time (up to 61.1%); the tag comparator can affect the cache access time for about 9.5%. This paper improved the existing cache access time model in which tag comparator gets insufficient attention. Based on the growing trend of the large last level cache (L3C) capacity in multi-core processors, the advantages of eDRAM on power and area make it more attractive. The simulation shows that, for L3C with large capacities (1MB, 4MB and larger than 16MB), the access time of the eDRAM cache is less than the SRAM cache for 8.1% (1MB) to 53.5% (512MB), supporting that eDRAM is a better choice for LLC in future 3D multi-core processors.