| 一种高频真对数放大器的设计 |
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| 引用本文： | 唐丽均,周熙,易文翠. 一种高频真对数放大器的设计[J]. 重庆邮电大学学报(自然科学版), 2006, 18(6): 683-685 |
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| 作者姓名： | 唐丽均 周熙 易文翠 |
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| 作者单位： | 重庆通信学院,网络与嵌入式系统实验室,重庆,400035 |
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| 摘 要： | 高频真对数放大器设计采用直流耦合放大器，运用4条增益路径的并联求和结构，提供了分段逼近的对数响应，有工作频率高、动态范围大、对数误差小等良好的性能，能很好地减少线路噪声。
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| 关 键 词： | 真对数放大器 并联求和 对数响应 |
| 文章编号： | 1004-5694(2006)06-0683-03 |
| 收稿时间： | 2006-03-06 |
| 修稿时间： | 2006-03-06 |
Design of a high frequency true logarithmic amplifier |
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| TANG Li-jun,ZHOU Xi,YI Wen-cui. Design of a high frequency true logarithmic amplifier[J]. Journal of Chongqing University of Posts and Telecommunications, 2006, 18(6): 683-685 |
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| Authors: | TANG Li-jun ZHOU Xi YI Wen-cui |
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| Affiliation: | Network and Embedded System Research Center, Chongqing Communication College, Chongqing 400035, P.R.China |
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| Abstract: | The design of a high frequency true logarithmic amplifier adopts a DC coupling amplifier; it uses a parallel summation architecture with four gain paths and provides a piecewise approximate logarithmic response. It has some good performance, such as high frequency, wide dynamic range and less logarithmic response error, which can decrease the linear noise. |
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| Keywords: | true logarithmic amplifier parallel summation logarithmic response |
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