| Deterministic Circular Self Test Path |
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| 作者单位： | Key Laboratory of Computer System and Architecture Institute of Computing Technology Chinese Academy of Sciences，Key Laboratory of Computer System and Architecture，Institute of Computing Technology Chinese Academy of Sciences，Key Laboratory of Computer System and Architecture，Institute of Computing Technology Chinese Academy of Sciences，Beijing 100080，China Graduate School of Chinese Academy of Sciences，Beijing 100080，China，Beijing 100080，China，Beijing 100080，China |
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| 基金项目： | 国家自然科学基金;国家重点基础研究发展计划(973计划) |
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| 摘 要： | Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits.
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Deterministic Circular Self Test Path |
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| WEN Ke,HU Yu,LI Xiaowei. Deterministic Circular Self Test Path[J]. Tsinghua Science and Technology, 2007, 12(Z1): 20-25 |
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| Authors: | WEN Ke HU Yu LI Xiaowei |
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| Abstract: | Circular self test path (CSTP) is an attractive technique for testing digital integrated circuits(IC) in the nanometer era, because it can easily provide at-speed test with small test data volume and short test application time. However, CSTP cannot reliably attain high fault coverage because of difficulty of testing random-pattern-resistant faults. This paper presents a deterministic CSTP (DCSTP) structure that consists of a DCSTP chain and jumping logic, to attain high fault coverage with low area overhead. Experimental results on ISCAS'89 benchmarks show that 100% fault coverage can be obtained with low area overhead and CPU time, especially for large circuits. |
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| Keywords: | very large scale integration (VLSI) test built-in-self-test (BIST) circular self test path deterministic |
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