| Hardwired Logic and Multithread Design in Network Processors |
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| 作者姓名： | 李旭东 徐扬 刘斌 王小军 |
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| 作者单位： | [1]DepartmentofComputerScienceandTechnology,TsinghuaUniversity,Beijing100084,China [2]SchoolofElectronicEngineering,DublinCityUniversity,Dublin9,Ireland |
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| 基金项目： | Supported by the National High-Tech Research and Development (863) Program of China (No. 863-300-01-99) and the National Natural Science Foundation of China (No. 60173009) |
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| 摘 要： | High-performance network processors are expected to play an important role in future highspeed routers, This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation.
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| 关 键 词： | 硬线逻辑 多线程设计 网络程序 IP头部程序 单线程 IPv4 |
Hardwired Logic and Multithread Design in Network Processors |
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| LI Xudong,XU Yang,LIU Bin,WANG Xiaojun.Hardwired Logic and Multithread Design in Network Processors[J].Tsinghua Science and Technology,2004,9(2):207-212. |
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| Authors: | LI Xudong XU Yang LIU Bin WANG Xiaojun |
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| Institution: | LI Xudong,XU Yang,LIU Bin,WANG Xiaojun Department of Computer Science and Technology,Tsinghua University,Beijing 100084,China, School of Electronic Engineering,Dublin City University,Dublin 9,Ireland |
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| Abstract: | High-performance network processors are expected to play an important role in future high-speed routers. This paper focuses on two representative techniques needed for high-performance network processors: hardwired logic design and multithread design. Using hardwired logic, this paper compares a single-thread design with a multithread design, and proposes general models and principles to analyze the clock frequency and the resource cost for these environments. Then, two IP header processing schemes, one in single-thread mode and the other in double-thread mode, are developed using these principles and the implementation results verified the theoretical calculation. |
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| Keywords: | network processor (NP) hardwired logic multithread IP header processing |
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