QC-eIRA码的构造及其变码率编码器FPGA实现

针对非规则重复累积码(extended irregular repeat-accumulate， eIRA)校验矩阵中H_1矩阵的随机性，提出采用有限域构造H_1矩阵的方法，并构造出了几种高码率码型。新构造码型既保留了eIRA码特殊的结构，同时又具有准循环LDPC码(quasi-cyclic low density parity check codes， QC-LDPC)的特点。仿真结果表明，当码长达到8175时，新构造码型的性能明显优于QC-LDPC码，在中长码长时表现出较好的性能。基于新码型结构特点，设计通过读写随机存储器(random-access memory，RAM)实现校验位计算的编码器硬件架构，采用Verilog HDL在Virtex 4 xc4vlx60芯片上实现了编码器，结果显示，相比于基于移位累加器组的传统QC-LDPC码，新的编码架构占用的硬件资源大幅降低，且更利于灵活实现变码率编码。

Construction of QC-eIRA codes and the FPGA implementation of its multi-rate encoder

A new construction method of H_1 based on finite fields is proposed in order to eliminate the randomness of H_1 matrix in extended irregular repeat-accumulate(eIRA)codes, and several high rate codes are constructed. The new codes not only retain the special structure of eIRA codes, but also have the characteristics of QC-LDPC codes. The simulation results show that the performance of the codes is better than QC-LDPC codes when the code length reaches 8175, and the codes have better performance when they are at moderate or long frame length. In addition,an encoding architecture for the calculation of check bits through read-write operations of RAMS is designed, which is implemented with Verilog HDL language on the chip of Virtex 4 xc4vlx60. Compared with the typical encoding architecture of QC-LDPC codes based on shift register, the new one saves more hardware resource and is easier to implement multi-rate encoder.