一种改进的QC-LDPC码及其编码器FPGA实现

为了提高低密度准循环奇偶校验码（quasi-cyclic low density parity check codes，QC-LDPC）的编码码率灵活性和降低该码的实现复杂度，提出了一种改进的 QC-LDPC 码构造方法，并通过构造校验矩阵设计出了几种高码率码型，仿真结果表明该码在中、长帧长时性能优于相近参数的传统 QC-LDPC 码；针对该码型设计了一种基于随机存取存储器（random-access memory，RAM）的编码器硬件架构，通过存储地址指针实现对校验矩阵的存储，使得编码器能灵活地实现变码率和变帧长编码。采用 verilog 硬件描述语言在 Spartan-3 XC3S1500芯片上实现了编码器。综合结果显示：新的硬件编码架构较基于移位寄存器的传统 QC-LDPC 码的编码器硬件架构，在编码延时保持相同而硬件资源大幅降低的情况下，编码器系统的最高频率达到了225．174 MHz，能满足高速编码需求。

An improved structure of QC-LDPC codes and its FPGA encoder implementation

In order to increase encoding rate flexibility and reduce its operation complexity,an improved structure of QC-LDPC codes is proposed,and several high rate codes were designed.Simulation result shows that the performance of the improved LDPC codes is better than that of conventional QC-LDPC codes in moderate and long frame length.An encoding architecture based on RAM is designed.The encoder stores the check matrix by storing address-pointers,thus multi-rate encoding is flexible.The encoder is implemented with Verilog HDL language on the chip of Spartan 3 XC3S1500.Synthesis reports show that the systems maximum frequency is 225.174 MHz with less resource and the same encoding time-delay of normal QC-LDPC encoder based on shift-register.