集成填充的可重构杂凑算法电路设计与实现

针对国内现有杂凑算法实现缺乏填充电路，已有设计又对SHA3算法标准不支持的问题，本文设计支持了MD5、SHA1、SM3、SHA2系列和SHA3系列5类共11个常见杂凑算法的完整电路.通过对2类填充规则6种填充位宽的分析，划分了不同的状态完成填充工作.通过对各个算法运算电路特征的分析，充分考虑运算单元资源的复用，设计了可重构的运算电路.集成了从算法的填充到输出的完整电路.在55 nm工艺库综合下相比较软件填充的方式，SM3、SHA2_384、SHA2_512 3个算法性能分别提高11%，22%，22%. 

Design and Implementation of Integration Padding Reconfigurable Hash Algorithm Circuit

In view of the lack of filling circuits in the implementation of existing domestic hash algorithms, and the existing designs do not support the SHA3 algorithm standard, a complete circuit was designed to support 11 common hash algorithms in 5 categories, including MD5, SHA1, SM3, SHA2 and SHA3 series. Firstly, analyzing 2 types of filling rules and 6 filling bit widths, the filling process was arranged with different states. Then, considering the characteristics of each arithmetic operation circuit and the reuse of operation unit resources, a reconfigurable operation circuit was designed. Finally, a complete circuit was integrated from algorithm filling to output. Compared with the software filling method under the synthesis of 55nm process library, the performance of SM3, SHA2 _ 384, and SHA2 _ 512 can be improved by 11%, 22% and 22% respectively.