可用于快速稳定PLL的低时钟抖动VCO设计

设计了一种基于电流控制逻辑（CSL）架构的650MHz环型压控振荡器(VCO),对传统的共源共栅结构偏置电路作了进一步的改善,加了一个电压增益较大的放大器构成有源负反馈以提高抗电源噪声的能力.同时也提出了一种阻尼因子控制电路结构,使该VCO可用于快速稳定的锁相环(PLL).该VCO采用和舰0.18μm双阱CMOS工艺仿真,在频率为20MHz、峰—峰值为200mV的高频电源噪声下，其峰-峰抖动和RMS抖动分别为22.649ps和7.793ps。该VCO输出频率为650MHz，占空比约为52%，增益(Kvco)为925.88MHz/V，线性度良好，在1.8V的直流电源下功耗约为0.7mw。

The Design of Low-Jitter VCO for fast-locked PLL

A 650MHz voltage-controlled oscillator (VCO) based on current steering logic structure is presented.For the improvement of conventional cascode bias circuit a amplifer with a larger voltage gain is added to it, and constitutes a new type active-feedback structure with better power supply noise rejection ability.A damping-factor-control circuit is also proposed, which maked this VCO suitable for fast-locked PLL.A simulation is conducted with HEJIAN 0.18μm twin-well technology. The peak-peak jitter and RMS(Root-Mean-Square) jitter are respectively 22.649ps and 7.793ps under the high frequency power supply noise with a 20MHz, 0.2V peak-peak amplitude. Still, the VCO output frequency is 650MHz with duty cycle of about 52% and gain (Kvco) of 925.88MHz/V, and this VCO has a good linearity between Kvco and the control voltage. And the power dissipation is about 0.7mw under 1.8V dc power supply.