| 对一种洗衣机控制器的FPGA设计改进 |
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| 引用本文： | 司孝平,赵严峰. 对一种洗衣机控制器的FPGA设计改进[J]. 佳木斯大学学报, 2006, 24(3): 356-359 |
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| 作者姓名： | 司孝平 赵严峰 |
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| 作者单位： | 华北水利水电学院信息工程系,河南,郑州,450011;黄淮学院电子科学系,河南,驻马店,463000 |
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| 摘 要： | 针对一种洗衣机控制器的FPGA的设计的不尽完善之处进行了改进.用ModelSim6.0对改进后控制器的verilogHDL代码进行了前后仿真,并在伟福EDA6000仿真系统实验仪上实现了此控制器.
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| 关 键 词： | FPGA设计 verilog HDL 仿真 洗衣机控制器 |
| 文章编号： | 1008-1402（2006）03-0356-04 |
| 收稿时间： | 2006-04-27 |
| 修稿时间： | 2006-04-27 |
Improvement on the Design of a Washer Controller Basing on FPGA |
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| SI Xiao-ping,ZHAO Yan-feng. Improvement on the Design of a Washer Controller Basing on FPGA[J]. Journal of Jiamusi University(Natural Science Edition), 2006, 24(3): 356-359 |
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| Authors: | SI Xiao-ping ZHAO Yan-feng |
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| Affiliation: | 1. North China University of Water Conservancy and Electric Power, Zhengzhou 450011, China; 2.Huanghuai Colledge, Zhumadian 463000, China |
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| Abstract: | The Improvement on design of a Washer Controller Basing on FPGA was carried out.Both functional and timing simulation to the verilog HDL source code for the washer controller were carried out with the ModelSim 6.0.And this washer controller was implemented on the EDA6000 System for Development of EDA made by Nanjing Wave Corp. |
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| Keywords: | verilog HDL |
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