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无线电监测接收机中的DDC研究
引用本文:李志军,安建平,孙磊.无线电监测接收机中的DDC研究[J].北京理工大学学报,2008,28(10):906-909.
作者姓名:李志军  安建平  孙磊
作者单位:北京理工大学,信息科学技术学院电子工程系,北京,100081;北京理工大学,信息科学技术学院电子工程系,北京,100081;北京理工大学,信息科学技术学院电子工程系,北京,100081
摘    要:提出了一种高效数字下变频器(DDC)实现方法. 基于4倍中频采样技术和多相抽取半带滤波结构改进的高效DDC实现结构,相当于仅使用了一个多相抽取半带滤波器实现了I,Q两路信号的输出,降低了运算复杂度,资源节省79%,功耗降低约60mW. 设计实例验证了该方法的正确性与高效性.

关 键 词:数字下变频器  多相结构  半带抽取滤波器  4倍中频采样
收稿时间:2007/12/27 0:00:00

Digital Down Converter(DDC) in Radio Monitoring Receivers
LI Zhi-jun,AN Jian-ping and SUN Lei.Digital Down Converter(DDC) in Radio Monitoring Receivers[J].Journal of Beijing Institute of Technology(Natural Science Edition),2008,28(10):906-909.
Authors:LI Zhi-jun  AN Jian-ping and SUN Lei
Institution:Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China;Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China;Department of Electronic Engineering, School of Information Science and Technology, Beijing Institute of Technology, Beijing 100081, China
Abstract:An improved efficient implementation method of digital down converter(DDC) in radio monitoring receivers is presented.Based on the sampling technique in which the sampling frequency is 4 times as high as the intermediate frequency and the use of polypahse decimation half band filter architecture,the improved architecture of high-efficiency DDC can be realized by using just one polyphase decimation half band filter to acquire the outputs of in-phase and quadrature in some sense.The improved method decreases the complexity of computation,reduces the burden of calculation and accumulated error.Resources of FPGA is saved 79% and the power consumption of the system is reduced about 60 mW.One design example is given and the results proved the validity and efficiency of the improved DDC structure.
Keywords:digital down converter(DDC)  polyphase structure  half band decimation filter  4-times-IF sampling
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