| 多元逻辑电路(DYL)线性“与或”门均匀性的研究 |
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| 引用本文： | 马平西,魏希文,邹赫麟. 多元逻辑电路(DYL)线性“与或”门均匀性的研究[J]. 大连理工大学学报, 1992, 0(4) |
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| 作者姓名： | 马平西 魏希文 邹赫麟 |
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| 作者单位： | 大连理工大学物理系(马平西,魏希文),大连理工大学物理系(邹赫麟) |
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| 摘 要： |
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| 关 键 词： | 逻辑电路 均匀性 误差理论/线性“与或”门 |
Study of uniformity of multicell-type logic circuit (DYL) linear "and/or" gates |
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| Ma Pingxi,Wei Xiwen,Zou Helin. Study of uniformity of multicell-type logic circuit (DYL) linear "and/or" gates[J]. Journal of Dalian University of Technology, 1992, 0(4) |
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| Authors: | Ma Pingxi Wei Xiwen Zou Helin |
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| Abstract: | Comparing the theoretical ana1ysis with the experimental results the authors have proved that the uniformity of linear "and/or" gates mainly depends on imput voltage and load resistance. When imput voltage is low, the uniformity changes a little with the load resistance. When imput voltage is high, the smaller the load resistance is, the more obviously the uniformity changes with imput voltage. |
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| Keywords: | logic circuits,uniformity,error theory/linear " and/or" gates |
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