| FIR数字滤波器的FPGA实现 |
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| 引用本文： | 陈晓勇,陈建平,陆旦前. FIR数字滤波器的FPGA实现[J]. 南通大学学报(自然科学版), 2007, 6(2): 91-94 |
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| 作者姓名： | 陈晓勇 陈建平 陆旦前 |
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| 作者单位： | 南通大学,计算机科学与技术学院,江苏,南通,226019;南通大学,计算机科学与技术学院,江苏,南通,226019;南通大学,计算机科学与技术学院,江苏,南通,226019 |
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| 摘 要： | 介绍了采用加法器树和线性相位结构在FPFA上实现FIR数字滤波器的方法,并通过Verilog HDL用Quartus II进行了仿真.相对于采用传统的移位相加乘法器和直接型结构的FIR滤波器设计,这种实现方式在性能上有明显的优势,使执行效率得到了较大提高.尤其在滤波器的阶数较大的情况下,优势会更明显.
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| 关 键 词： | FIR数字滤波器 FPGA Quartus Ⅱ 线性相位 |
| 文章编号： | 1673-2340（2007）02-0091-04 |
| 修稿时间： | 2006-08-11 |
Implementation of a FIR Filter with FPGA |
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| CHEN Xiao-yong,CHEN Jian-ping,LU Dan-qian. Implementation of a FIR Filter with FPGA[J]. Journal of Nantong University (Natural Science Edition), 2007, 6(2): 91-94 |
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| Authors: | CHEN Xiao-yong CHEN Jian-ping LU Dan-qian |
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| Affiliation: | School of Computer Science, Nantong University, Nantong 226019, China |
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| Abstract: | This paper introduced how to design a FIR digital filter by using an add-tree function and the linear-phase architecture with FPGA.The implementation was simulated through the Verilog HDL in Quartus II.Compared with the traditional way of using shift-adder function and direct FIR model,this way is better.Especially when the orders of the filter increase,the advantage will be more obvious. |
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| Keywords: | FPGA |
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