高速低耗BiCMOS OC门及其线与逻辑系统

为了满足高速度、低功耗数字逻辑系统的应用需求，运用改进电路内部结构和优化选取器件参数的方法，设计了4种双极互补金属氧化物半导体集电极开路（BiCMOS OC）门，并且用它们构成了线与逻辑系统；藉助两个BiCMOS OC门线与系统推导出其上拉电阻RL的计算式；对所设计的4种BiCMOS OC门和一种传统的TTL OC门线与系统进行了仿真试验和硬件电路试验．长工验数据和分析结果表明，所设计的BiCMOS OC门线与系统的电源电压均可为2．6—4．0V，工作速度与TIL OC门线与系统相接近，在60MHz测试条件下它们的功耗比TTL OC门减少4．77—5．68mW，且它们的延迟一功耗积平均降低了45．5％．

Several high-speed and low-consumption BiCMOS OC gates and their wired-AND logic systems

To meet the application needs of high-speed and low-energy consumption digital systems,several kinds of BiCMOS open collector(OC)gates were designed by means of modifying inner structure and by using optimal parameters,with which some wired-AND logic systems were connected,and the common upward-resistance RL expressions of these systems were deduced from 2 wired-AND equivalent circuits.The related analysis,simulation and the circuit experiment results have shown that the designed BiCMOS wired-AND logic systems can work properly within 2.6-4.0 V,the average speed is close to that of conventional TTL OC gate,the power consumption is lower than that of the conventional gate by 4.77-5.68 mW,and the delay-consumption product is reduced by an average of 45.5% as compared to the conventional gate at 60 MHz.