用多路数字FIR滤波器实现动目标多卜勒反射波跟踪的硬件电路设计

讨论了飞行体生地杂波中检测运动目标反射波的基本原理；并提出了一种对动目标反射波进行自动跟踪的数字系统，本文着重讨论该跟踪数字系统的硬件电路设计及其工作原理．     

高速数据采集系统中的孔径抖动

研究高速数据采集系统中的孔径抖动对系统信噪比的影响．通过对高速ADC采样保持电路的结构与时域响应的描述，对孔径抖动的成因以及孔径抖动误差与输入信号频率的关系进行了分析，并在此基础上对孔径抖动对数据采集系统信噪比的影响进行了分析与计算仿真．结果表明，孔径抖动引起的孔径误差随着高速数据采集系统输入信号频率的升高而增大，由此将引起系统信噪比曲下降．因此在系统设计中，ADC的孔径抖动及其它可能引入孔径抖动的因素都应给予充分考虑．     

并行模拟数字转换器系统设计与实现

介绍了一种并行模拟数字转换器系统的设计与实现,该系统采用4片A／D并行交替采样,采样速率可达200MHz,分辨率可达到12bit。给出了方案构成的硬件系统设计,并详细阐述了各硬件系统平台的具体构成。针对通道失配问题,在FPGA内部实现了通道失配误差的测量。该系统的实现对超高速并行采样技术的研究具有一定的指导意义,且该平台的构建在工程应用上具有一定的通用性。     

MU-MIMO单比特ADC系统中软输出检测算法

低精度量化技术能解决毫米波通信射频链高能耗问题而使相关的接收技术受到广泛关注.本文针对应用于单比特量化上行多用户多输入多输出(multiuser multiple input multiple output,MU-MIMO)系统的软输出检测(soft output detection,SOD)算法计算复杂度高的问题,针...     

基于ADC0809的模数转换应用举隅

模数转换器通常定位为单片机的外部RAM单元.介绍了ADC0809与AT89S51接口电路的几种方法,分析了各种接口电路的特点及其扼要的启动程序.     

Adaptive Digital Calibration of Amplifier Finite Gain Effects and C-ratio Matching Errors for MASH Modulators

Cascaded sigma-delta (MASH) modulators for higher order oversampled analog-to-dlgital conversionrely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents an adaptive algorithm and implementation architectures for digital correction of such analog imperfections. Behavioral simulations on 1-1-1 oversampled converters demonstrate over 10dB improvements in signal-to-noise an dover 20 dB improvements in dynamic range performance.     

Anti-saturation block adaptive quantization algorithm for SAR raw data compression over the whole set of saturation degrees

In order to improve the performance of block adaptive quantization (BAQ) when the output of the analog to digital converter (ADC) is saturated, this paper proposes an anti-saturation BAQ algorithm. First, the concept of the standard deviation of the output signal (SDOS) of the ADC is proposed. Also, unlike traditional normalization processing, SDOS is used and the mapping between SDOS and the average signal magnitude is deduced. Second, the saturation term is introduced to the Lloyd–Max quantizer and an optimal non-uniform scalar quantizer for saturated SAR raw data quantization is proposed. After this, the implementation scheme for the proposed algorithm using an FPGA is analyzed in detail. Third, the relationships among the saturation degree of the signal, the peak-topeak value of the ADC, standard deviation of the input and output signal of the ADC and the average signal magnitude are deduced. Based on these relationships, a power compensation decoder is designed for encoding. Numerical experiment results based on ERS-1 and the simulated data show that the performance of the proposed algorithm is better than that of BAQ.     

Op Amp共享与移除取样保持电路之低功率管线式ADC芯片设计

以TSMC 0.18μm CMOS制程实现10住元(10-bit)、每秒取样2×10<'7>次、操作电压1.8 V的管线式(pipeline)模拟数字转换器(ADC)芯片.本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗.此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm<'2>,芯片功耗为29.2 mW.