具有错误探测和纠正功能的电路设计策略

为了克服传统处理器设计方法采用最坏情况来确定电路的工作频率带来的性能(吞吐率)损失,人们开始采用具有探测错误和纠正错误功能的电路设计方法。该文在已有的探测错误、纠正错误电路基础上,提出了一种针对具有延时错误纠错功能的电路的设计策略。该方法通过计算电路的延时错误概率函数,得出在一定电源电压下使得电路达到最大吞吐率的工作频率。模拟实验结果表明,该方法可以求得使电路获得最大吞吐率的工作频率。     

Probabilistic Delay Fault Model for DVFS Circuits

Decreasing the power supply voltage in dynamic voltage frequency scaling to save power consumption may introduce extra delays in CMOS circuits, which may cause errors. This paper presents the probabilistic delay fault model (PDFM), which describes the probability of an error occurring as a function of the power supply voltage and the clock period in synchronous CMOS circuits. In a wide range of applications (graphic, video, digital filtering, etc.), errors occurring with low probability and not remaining for a long time are acceptable. For combinational circuits which have long critical paths with low probability of excitation, a performance increase is achieved with a certain rate of errors determined by the PDFM compared with the traditional design which considers the worst case. The PDFM applied to array multipliers and ripple carry adders shows the agreement of the predicted probabilities with simulated delay histograms to support the practicality of using the PDFM to select power supply voltage and clock period in dynamic voltage frequency scaling circuits with tolerable error rates.