迈克尔逊干涉仪实验常见问题的分析与处理

针对在迈克尔逊实验教学中学生对等倾干涉判断不准确、等倾干涉圆环的调节过程欠当和干涉条纹"冒出"与"陷入"的问题进行分析,提出了解决方案.     

物体密度测量实验方法的改进

基于桥式电路测量原理的分析,针对目前大学物理物体密度测量实验,设计了一种桥式电路测量方法.将密度测量与电学结合,可实现计算机在线实时检测,提高了学生的动手能力和综合能力.     

量纲分析及其在物理实验中的应用

基于对量纲基本概念和量纲分析法基本原理的分析，探讨了量纲分析在物理实验中的应用。在物理实验教学中，采用物理量的量纲表示可以方便单住换算，利用量纲基本规则可判断物理公式的正确性，通过量纲的分析可使寻找物理量间复杂关系或规律变得简单。     

EXCEL在物理实验数据处理中的应用

EXCEL软件具有强大的数据处理、分析、统计功能，将EXCEL用于大学物理实验教学中的实验数据处理，不用编程，学生易学易用，本文结合实例介绍了用EXCEL处理实验数据的方法。     

作图法处理实验数据的不确定度评定

作图法是物理实验的数据处理方法之一。在给出作图法的一些作图要求的基础上,认为将坐标轴进行合理分度,通过选轴作图法的数据处理进行不确定度的评定,可提高实验精度,并以单摆实验为例进行了实例分析。     

Design of 15 Gb/s inductorless limiting amplifier with RSSI and LOS indication in 65nm CMOS

A limiting amplifier IC implemented in 65 nm CMOS technology and intended for high-speed optical fiber communications is described in this paper.The inductorless limiting amplifier incorporates5-stage 8 dB gain limiting cells with active feedback and negative Miller capacitance,a high speed output buffer with novel third order active feedback,and a high speed full-wave rectifier.The receiver signal strength indictor(RSSI) can detect input signal power with 33 dB dynamic range,and the limiting amplifier features a programmable loss of signal(LOS) indication with external resistor.The sensitivity of the limiting amplifier is 5.5mV at BER = 10 ~(-12) and the layout area is only 0.53 ×0.72 mm because of no passive inductor.The total gain is over 41 dB,and bandwidth exceeds12 GHz with 56 mW power dissipation.     

在物理实验教学中培养学生的科学素质

实验教学是培养学生科学素质的重要途径。本文从激发学生的学习兴趣、培养学生的观察能力、实验能力、科学思维方法、科学态度等五个方面探讨了在物理实验教学中如何对学生进行素质教育的问题     

Verilog HDL modeling and design of 10Gb/s SerDes full rate CDR in 65nm CMOS

Phase locked loop （PLL） is a typical analog-digital mixed signal circuit and a method of conducting a top level system verification including PLL with standard digital simulator becomes especially significant. The behavioral level model （BLM） of the PLL in Verilog-HDL for pure digital simulator is innovated in this paper, and the design of PLL based clock and data recovery （CDR） circuit aided with jitter attenuation PLL for SerDes application is also presented. The CDR employs a dual-loop architecture where a frequency-locked loop acts as an acquisition aid to the phase-locked loop. To simultaneously meet jitter tolerance and jitter transfer specifications defined in G. 8251 of optical transport network （ ITU-T OTN） , an additional jitter attenuation PLL is used. Simulation results show that the peak-to-peak jitter of the recovered clock and data is 5.17ps and 2.3ps respectively. The core of the whole chip consumes 72mA current from a 1.0V supply.