论“时-空”间隔不变变换——兼与《相对绝对论》一文作者商榷

本文给出零时空间隔不变变换式和非零时空间隔不变变换式的导出过程，同时阐明两种变换式的物理含义．     

CSC5087 SC8870与单片机的接口及应用

在介绍通讯集成电路ＣＳＣ５０８７和ＳＣ８８７０的基础上，给出了与单片机的接口方法和应用。     

钟控判优逻辑电路的研究

在集成数字逻辑电路中,经常遇到多个事件同时或先后请求操作的现象,电路必须对这些事件进行管理、判断和服务,从而出现了各种类型的判优逻辑电路.针对钟控判优逻辑电路进行了分类、定义、解析,列举出相应的电路图,分析了它们的工作过程,并就电路的性能进行了论述,为电路设计人员提供了有效实用具体的设计方案.     

Jurassic radiation of large Branchiopoda (Arthropoda: Crustacea) using secondary structure-based phylogeny and relaxed molecular clocks

The phylogenetic relationships of large Branchiopoda have been one of the most controversial issues in the studies of Crustacea. This study attempts to tackle systematic problems concerning “conchostracan” and anostracan evolution, by analyzing ribosomal RNA sequences of both mitochondrial (12S) and nuclear genes (18S). Phylogenetic trees are reconstructed with these data from 27 genera belonging to 18 families, using maximum parsimony procedures, maximum likelihood, and Bayesian analysis coupled with Markov chain Monte Carlo (MCMC) techniques under mixed and doublet models. The results suggest that Diplostraca (Conchostraca+Cladocera) form a monophyletic group, with Spincaudata and Cladoceromorpha being sister groups and Laevicaudata a basal lineage of Diplostraca; Notostraca and Diplostraca together form the monophyletic Phyllopoda. Within Diplostraca, Conchostraca is paraphyletic in contrast to the traditional systematic classification. Relaxed molecular clock analysis, using multiple fossil calibration points, indicates that the conchostracan three genera—Imnadia, Caenestheriella， and Caenestheria, emerged during Jurassic; most anostracan groups, such as Polyartemiinae, Chirocephalinae, Branchinectidae, and Streptocephalidae, experienced an adaptive radiation during Jurassic, and probably related with the fragmentation of the Pangea supercontinent.     

异步时序逻辑电路设计的一种简明方法

提出了一种异步时序电路设计的新方法：时钟信号与次态卡诺图联立法．根据时钟信号填写次态卡诺图，当触发器满足时钟信号时其次态由状态转换图决定，否则其次态为约束项．据此可方便求出驱动方程并判断自启动．     

网络交通分布式模拟乐观同步算法研究

基于分布式网络环境，运用并行模拟领域的最新研究成果，对路网交通流分面式并行模拟中如何实现处理内部的时钟同步问题进行深入研究，提了了定时段扫描的乐观同步算法，以确保模拟中事件逻辑关系的一致性。最后以含9个节点的路网为例，运用该同步算法进行模拟应用，对路网串行、并行模拟的效率和效益进行了对比分析，从根本上体现了路网颁式模拟研究的意义。     

基于双边沿触发的低功耗触发器逻辑设计

从消除时钟冗余,提高时钟利用率以达到降低功耗的思想出发,提出基于双边沿触发的触发器的逻辑设计。新构建的双边沿触发器逻辑功能正确,时钟利用率高,功耗降低显著.     

Maximum Likelihood Estimation of Clock Synchronization Error in OFDM System

IntroductionForhigh ratedatatransmission ,robustnessofimpulsenoise,andfastfrequencyselectivefading ,orthogonalfrequencydivisionmultiplexingmodulationhasbeenadoptedfordigitalvideobroadcastingforterrestrial[1] andintegratedservicedigitalbroadcastingforterrestrial[2 ] ,respectively .However,ascomparedtosingle carriersystems,OFDMsystemsaremoresensitivetocarrierfrequencyoffsetandclocksynchronizationerror,onlytheperfectsynchronizationbetweenthetransmitterandreceivercanassuretheindependencybetweenea…     

应用于FPGA芯片时钟管理的锁相环设计实现

设计了一种嵌入于FPGA芯片的锁相环,实现了四相位时钟、倍频、半整数可编程分频、可调节相位输出功能,满足对于FPGA芯片时钟管理的要求.锁相环采用了自偏置结构,拓展了锁相环的工作范围,缩短了锁定时间,其阻尼系数以及环路带宽和工作频率的比值都仅由电容的比值决定,有效地减小了工艺、电压、温度等对电路的影响.锁相环采用0.18μm CMOS数字工艺,嵌入复旦大学自主研发的FPGA芯片FDP-Ⅱ,经过流片验证,实现了工作频率范围10~600 MHz,整体电路功耗仅为29 mW,锁定时间小于4μs,峰峰值抖动小于±145 ps.     

ReSim:一个面向可重构处理器的仿真平台

针对可重构处理器ReMAP(reconfigurable multimedia array processor)面向视频高清编解码提出的灵活互联、计算资源密集、易于扩展的结构优化需求,提出了一个基于模块化分层设计、时钟周期精确的可重构处理器仿真平台ReSim.该仿真器基于3级软件框架层次搭建,设计了可快速仿真多种互联结...