基于队列的处理器亲和机制及在网络转发中的应用

提出一种新的基于多报文队列的处理器亲和机制,与传统基于网络接口的亲和机制相比,消除了多处理器对共享资源的竞争,优化了处理器的CACHE行为,降低了互斥锁的影响范围,能够有效提升多核处理器系统的网络转发处理能力.试验结果显示,在复杂网络环境下,基于队列的亲和机制报文转发性能较传统基于接口的亲和机制提高了1.8倍.     

OpenMP多核技术研究及其在遗传算法中的应用

介绍了OpenMP的并行执行原理和语言规范,重点讨论了OpenMP的循环并行化、迭代相关、数据共享、任务调度等问题,最后使用OpenMP技术优化了遗传算法,并进行了性能的对比.     

High-Performance Packet Classification on Multi-Core Network Processing Platforms

Packet classification is crucial to the implementation of advanced network services that require the capability to distinguish traffic in different flows, such as access control in firewalls and protocol analysis in intrusion detection systems. This paper proposes a novel packet classification algorithm optimized for multi-core network processors. The proposed algorithm, AggreCuts, has an explicit worst-case search time with modest memory usage. The data structure of AggreCuts is flexible and well-adapted to different types of multi-core platforms. The algorithm on both Intel IXP2850 32-bit and Cavium OCTEON3860 64-bit multi-core platforms was implemented to evaluate the performance of AggreCuts. The experimental results show that AggreCuts outperforms the best-known existing algorithm in terms of memory usage and classification speed.     

雷电电磁脉冲场对多芯线的耦合效应研究

为研究多芯线短线缆在雷电电磁脉冲场辐照下终端负载的感应电压,利用WU-800型MARX源和有界波模拟器来模拟雷电电磁脉冲场,对多芯线进行辐照耦合试验。试验中通过改变试验条件,得到了不同雷电电磁脉冲波形、多芯线长度、辐射场与线缆夹角、线缆终端负载条件下多芯线终端负载的感应电压的变化规律。试验发现:雷电电磁脉冲的上升沿对线缆耦合电压幅值影响较大,脉宽对耦合电压影响较小;线缆长度对感应电压的幅值及响应频点有重要影响;电场极化方向对线缆终端响应幅值有较大影响,但并不改变响应波形;随着受测端负载阻值的增加,线缆感应电压也逐步增大,非受测端负载对线缆感应电压无影响。     

基于网络处理器的高性能入侵防护系统研究

提出一种基于网络处理器的入侵防护系统模型,该模型基于异构多核计算架构,采用通用x86/IA多核处理器作为应用和控制CPU,运行检测和控制模块,专用网络处理器作为协处理器实现网络层面的处理,两者之间通过PCIE实现高速通信,从而实现高效能、自适应、可扩展的入侵防护系统.用NFE-i8000网络处理器和Intel Xeon E5620四核八线程的通用处理器实现系统原型,并用PHAD异常检测系统作为入侵检测器进行了模拟实验.仿真结果表明,模型不但可提高系统性能,而且按协议类型进行负载均衡的检测结果比按五元组要好.     

多核计算环境下的LiDAR数据DEM内插方法研究

为了分析并提高在多核计算环境下大数据量激光雷达数据内插DEM效率问题,利用多线程技术,设计了在多核计算环境下DEM分块内插并行算法,讨论了并行算法的流程和技术要点,并实验分析了分块大小和搜索半径对并行算法的加速比影响.实验表明:在分块较小时,加速比与核数具有线性增长关系;而内插搜索半径越大,加速比越小,但影响不十分显著.总体上,多核并行算法一定程度上提高了DEM内插效率,但是会受到计算机内存速度的限制.     

计算机系统结构课程多核创新实验探索

在现有文献的基础上,电子科技大学计算机科学与工程学院研究了计算机系统结构课程中多核创新实验,体现在多核技术知识点在课程中的设计安排和多核创新实验的构建,并探讨了多核创新实验的设计目标。多核创新实验涵盖硬软件2个方面的实验内容:在FPGA芯片上设计多内核计算机系统及W indows/L inux多核多线程编程。该实验,以加深学生对多核知识点的理解掌握为根基,具有可编程逻辑器件、操作系统与多核新组合的创新特点。     

Cache performance optimization of irregular sparse matrix multiplication on modern multi-core CPU and GPU

This paper focuses on how to optimize the cache performance of sparse matrix-matrix multiplication （SpGEMM）.It classifies the cache misses into two categories：one is caused by the irregular distribution pattern of the multiplier-matrix,and the other is caused by the multiplicand.For each of them,the paper puts forward an optimization method respectively.The first hash based method removes cache misses of the 1 st category effectively,and improves the performance by a factor of 6 on an Intel 8-core CPU for the best cases.For cache misses of the 2nd category,it proposes a new cache replacement algorithm,which achieves a cache hit rate much higher than other historical knowledge based algorithms,and the algorithm is applicable on CELL and GPU.To further verify the effectiveness of our methods,we implement our algorithm on GPU,and the performance perfectly scales with the size of on-chip storage.     

A High Performance Multifrontal Code for Linear Solution of Structures Using Multi-Core Microprocessors

A multifrontal code is introduced for the efficient solution of the linear system of equations arising from the analysis of structures. The factorization phase is reduced into a series of interleaved element assembly and dense matrix operations for which the BLAS3 kernels are used. A similar approach is generalized for the forward and back substitution phases for the efficient solution of structures having multiple load conditions. The program performs all assembly and solution steps in parallel. Examples are presented which demonstrate the code’s performance on single and dual core processor computers.     

基于分布式共享内存的RTI通信机制研究

共享内存可以为运行于多核计算平台的进程间提供高效的通信方式,目前的HLA仿真运行支撑平台RTI主要采用基于TCP/IP的通信机制,不能充分发挥多核计算平台的核间高速共享内存通信优势.结合 RTI体系结构和多核的通信特点,提出了一种基于分布式共享内存的RTI通信机制——SMCM机制,该机制为每个盟员设立一个独立的消息接收共享内存区域,发送盟员通过向接收盟员内存区写数据实现消息发送,并基于信号量机制实现盟员进程间访问控制,避免了共享内存访问冲突,提高了盟员间可的通信效率.多核平台上的对象管理服务性能测试表明,与当前国际上普遍使用的pRTI相比,使用SMCM机制的RTI端对端通信延迟约为pRTI的1/3,吞吐量也明显高于pRTI.