Electronic transport in nanometre-scale silicon-on-insulator membranes

The widely used 'silicon-on-insulator' (SOI) system consists of a layer of single-crystalline silicon supported on a silicon dioxide substrate. When this silicon layer (the template layer) is very thin, the assumption that an effectively infinite number of atoms contributes to its physical properties no longer applies, and new electronic, mechanical and thermodynamic phenomena arise, distinct from those of bulk silicon. The development of unusual electronic properties with decreasing layer thickness is particularly important for silicon microelectronic devices, in which (001)-oriented SOI is often used. Here we show--using scanning tunnelling microscopy, electronic transport measurements, and theory--that electronic conduction in thin SOI(001) is determined not by bulk dopants but by the interaction of surface or interface electronic energy levels with the 'bulk' band structure of the thin silicon template layer. This interaction enables high-mobility carrier conduction in nanometre-scale SOI; conduction in even the thinnest membranes or layers of Si(001) is therefore possible, independent of any considerations of bulk doping, provided that the proper surface or interface states are available to enable the thermal excitation of 'bulk' carriers in the silicon layer.     

Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors

Over the past several years, the inherent scaling limitations of silicon (Si) electron devices have fuelled the exploration of alternative semiconductors, with high carrier mobility, to further enhance device performance. In particular, compound semiconductors heterogeneously integrated on Si substrates have been actively studied: such devices combine the high mobility of III-V semiconductors and the well established, low-cost processing of Si technology. This integration, however, presents significant challenges. Conventionally, heteroepitaxial growth of complex multilayers on Si has been explored-but besides complexity, high defect densities and junction leakage currents present limitations in this approach. Motivated by this challenge, here we use an epitaxial transfer method for the integration of ultrathin layers of single-crystal InAs on Si/SiO(2) substrates. As a parallel with silicon-on-insulator (SOI) technology, we use 'XOI' to represent our compound semiconductor-on-insulator platform. Through experiments and simulation, the electrical properties of InAs XOI transistors are explored, elucidating the critical role of quantum confinement in the transport properties of ultrathin XOI layers. Importantly, a high-quality InAs/dielectric interface is obtained by the use of a novel thermally grown interfacial InAsO(x) layer (~1?nm thick). The fabricated field-effect transistors exhibit a peak transconductance of ~1.6?mS?μm(-1) at a drain-source voltage of 0.5?V, with an on/off current ratio of greater than 10,000.     

Coherent signal amplification in bistable nanomechanical oscillators by stochastic resonance

Stochastic resonance is a counterintuitive concept: the addition of noise to a noisy system induces coherent amplification of its response. First suggested as a mechanism for the cyclic recurrence of ice ages, stochastic resonance has been seen in a wide variety of macroscopic physical systems: bistable ring lasers, superconducting quantum interference devices (SQUIDs), magnetoelastic ribbons and neurophysiological systems such as the receptors in crickets and crayfish. Although fundamentally important as a mechanism of coherent signal amplification, stochastic resonance has yet to be observed in nanoscale systems. Here we report the observation of stochastic resonance in bistable nanomechanical silicon oscillators. Our nanomechanical systems consist of beams that are clamped at each end and driven into transverse oscillation with the use of a radiofrequency source. Modulation of the source induces controllable switching of the beams between two stable, distinct states. We observe that the addition of white noise causes a marked amplification of the signal strength. Stochastic resonance in nanomechanical systems could have a function in the realization of controllable high-speed nanomechanical memory cells, and paves the way for exploring macroscopic quantum coherence and tunnelling.     

Ultrafast and direct imprint of nanostructures in silicon

The fabrication of micrometre- and nanometre-scale devices in silicon typically involves lithography and etching. These processes are costly and tend to be either limited in their resolution or slow in their throughput. Recent work has demonstrated the possibility of patterning substrates on the nanometre scale by 'imprinting' or directed self-assembly, although an etching step is still required to generate the final structures. We have devised and here demonstrate a rapid technique for patterning nanostructures in silicon that does not require etching. In our technique which -- we call 'laser-assisted direct imprint' (LADI) -- a single excimer laser pulse melts a thin surface layer of silicon, and a mould is embossed into the resulting liquid layer. A variety of structures with resolution better than 10 nm have been imprinted into silicon using LADI, and the embossing time is less than 250 ns. The high resolution and speed of LADI, which we attribute to molten silicon's low viscosity (one-third that of water), could open up a variety of applications and be extended to other materials and processing techniques.     

Al2O3衬底上多晶硅薄膜的外延和区熔再结晶

研究了陶瓷衬底上多晶硅薄膜的生长和区熔再结晶.利用快速热化学气相沉积(RTCVD)方法,在低成本的Al2O3衬底上沉积了重掺杂的致密多晶硅薄膜,薄膜的晶粒尺寸在微米级.经区熔再结晶(ZMR)后,薄膜的晶粒尺寸有了较大的提高,而且迁移率较高,这样的薄膜可以用作晶体硅薄膜太阳电池的籽晶层.最大的晶粒达到毫米量级,空穴迁移率超过50 cm2·V-1·s-1.在籽晶层上外延的活性层形貌与此类似.这些结果显示这种薄膜在光伏应用方面有较大的潜力.     

集成电路钝化层薄膜的纳米力学性质研究

利用等离子体增强化学气相淀积工艺在P型单晶硅（111）衬底上制备了厚度为70、150、450nm的SiO2薄膜和100、170、220nm的Si3N4薄膜,并使用纳米压入仪对薄膜进行了纳米力学测试与分析．薄膜在不同载荷下的硬度和弹性模量计算采用Oliver-Pharr方法．在测量两种薄膜的硬度时没有发现压痕尺寸效应．SiO2薄膜的弹性模量与压入深度的依赖关系不明显,但与薄膜厚度的依赖关系较明显,薄膜厚度的增加将导致弹性模量显著减小,而Si3N4的弹性模量与薄膜厚度的依赖关系不明显,但与压入深度的依赖关系较明显,会随着压入深度的增加而逐渐增加到某一定值．     

Patterning organic single-crystal transistor arrays

Field-effect transistors made of organic single crystals are ideal for studying the charge transport characteristics of organic semiconductor materials. Their outstanding device performance, relative to that of transistors made of organic thin films, makes them also attractive candidates for electronic applications such as active matrix displays and sensor arrays. These applications require minimal cross-talk between neighbouring devices. In the case of thin film systems, simple patterning of the active semiconductor layer minimizes cross-talk. But when using organic single crystals, the only approach currently available for creating arrays of separate devices is manual selection and placing of individual crystals-a process prohibitive for producing devices at high density and with reasonable throughput. In contrast, inorganic crystals have been grown in extended arrays, and efficient and large-area fabrication of silicon crystalline islands with high mobilities for electronic applications has been reported. Here we describe a method for effectively fabricating large arrays of single crystals of a wide range of organic semiconductor materials directly onto transistor source-drain electrodes. We find that film domains of octadecyltriethoxysilane microcontact-printed onto either clean Si/SiO(2) surfaces or flexible plastic provide control over the nucleation of vapour-grown organic single crystals. This allows us to fabricate large arrays of high-performance organic single-crystal field-effect transistors with mobilities as high as 2.4 cm(2) V(-1) s(-1) and on/off ratios greater than 10(7), and devices on flexible substrates that retain their performance after significant bending. These results suggest that our fabrication approach constitutes a promising step that might ultimately allow us to utilize high-performance organic single-crystal field-effect transistors for large-area electronics applications.     

中子辐照半绝缘硅衬底上的SOI技术

本文描述了一种新奇的 SOI 技术:中子辐照单晶硅形成半绝缘材料,经激光扫描退火恢复表面层的半导体特性并由此组成了 SOI 结构。在这个结构上我们制作了 n 沟 MOSFET。本文研究了这种半绝缘层的性质,这种技术的工艺流程和条件以及用这种方法制得的 MOS 器件的性能.     

中子辐照半绝缘硅衬底上的SOI技术

本文描述了一种新奇的SOI技术:中子辐照单晶硅形成半绝缘材料,经激光扫描退火恢复表面层的半导体特性并由此组成了SOI结构.在这个结构上我们制作了n沟MOSFET.本文研究了这种半绝缘层的性质,这种技术的工艺流程和条件以及用这种方法制得的MOS器件的性能.     

Silicon dots films deposited by spin-coating as a generated carrier addition layer of third generation photovoltaics

In this work, silicon ink composing of silicon powder and zinc oxide solution was formulated and spin-coated on quartz and n/p-Si substrates followed by drying the films under atmosphere at the temperature of 550°C. The results showed that this top-addition layer could be the highly promising layer for photo-generating carriers in third-generation photovoltaics to enhance blue-light absorption. X-ray diffraction and scanning electron microscopy techniques were used to study the presence of silic...     

聚3-己基噻吩聚合物薄膜晶体管稳定性

以单晶硅为衬底, 二氧化硅为栅介质层, 聚3-己基噻吩（P3HT）薄膜为半导体活性层, 金属Au为源、漏电极, 制备出聚合薄膜晶体管（PTFT）, 并对该器件特性进行了表征．研究了该器件在空气环境下的稳定性, 并对该器件在空气中的不稳定性机理进行了讨论．结果表明, 当器件曝露在空气中时, 随着曝露时间的增加, 器件的饱和漏电流明显增大, 阈值电压逐渐增加．空气中的水是影响器件特性变化的主要因素．通过采用光刻胶钝化处理可以有效地改善P3HT-PTFT器件空气中的稳定性, 并使器件的载流子迁移率提高3倍．     

Nanotechnology: high-speed integrated nanowire circuits

Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.     

Optimal design of label-free silicon“ lab on a chip” biosensors

This paper reported the optimal design of label-free silicon on insulator(SOI) "lab on a chip"biosensors.These devices are designed on the basis of the evanescent field detection principles and interferometer technologies.The well-established silicon device process technology can be applied to fabricate and test these biosensor devices.In addition,these devices can be monolithically integrated with CMOS electronics and microfuidics.For these biosensor devices,multi-mode interferometer(MMI) was employed to combine many stand-alone biosensors to form chip-level biosensor arrays,which enable realtime and label-free monitoring and parallel detection of various analytes in multiple test samples.This sensing and detection technology features the highest detection sensitivity,which can detect analytes at extremely low concentrations instantaneously.This research can lead to innovative commercial development of the new generation of high sensitivity biosensors for a wide range of applications in many fields,such as environmental monitoring,food security control,medical and biological applications.     

杂质纵向高斯分布UTBB-SOI MOSFET的虚拟阴极阈值电压解析模型

采用Sentaurus Process工艺仿真工具,验证了超薄硅膜内单次纵向离子注入并快速热退火后所实现的轻掺杂杂质分布符合高斯规律。设计杂质纵向高斯分布的轻掺杂纳米UTBB-SOI MOSFET,用虚拟阴极处反型载流子浓度来定义阈值电压的方法,为器件建立二维阈值电压解析模型。通过与Sentaurus Device器件仿真结果对比分析,发现:阈值电压模型能准确预测器件在不同掺杂、器件厚度和偏置电压下的阈值电压,正确反映器件的背栅效应,其模拟结果与理论模型相符。     

SOI双槽隔离结构的耐压特性

理论推导了绝缘体上硅(SOI)双槽隔离结构的耐压模型.该模型表明,在SOI双槽隔离结构中,因隔离氧化层压降的不均衡,高压侧隔离氧化层提前发生介质击穿,从而导致SOI双槽隔离结构的临界击穿电压小于理论值.增大沟槽纵横比和减小槽间距可以减弱隔离氧化层上压降的不均衡性,提高SOI双槽隔离结构的临界击穿电压.Sentaurus器件仿真软件的模拟结果和华润上华半导体有限公司0.5μm 200 V SOI工艺平台下的流片测试结果均证明,减小槽间距和增大沟槽纵横比是提高双槽隔离结构临界击穿电压的有效方法,同时也证明了该耐压模型的正确性.     

Cooling a nanomechanical resonator with quantum back-action

Quantum mechanics demands that the act of measurement must affect the measured object. When a linear amplifier is used to continuously monitor the position of an object, the Heisenberg uncertainty relationship requires that the object be driven by force impulses, called back-action. Here we measure the back-action of a superconducting single-electron transistor (SSET) on a radio-frequency nanomechanical resonator. The conductance of the SSET, which is capacitively coupled to the resonator, provides a sensitive probe of the latter's position; back-action effects manifest themselves as an effective thermal bath, the properties of which depend sensitively on SSET bias conditions. Surprisingly, when the SSET is biased near a transport resonance, we observe cooling of the nanomechanical mode from 550 mK to 300 mK--an effect that is analogous to laser cooling in atomic physics. Our measurements have implications for nanomechanical readout of quantum information devices and the limits of ultrasensitive force microscopy (such as single-nuclear-spin magnetic resonance force microscopy). Furthermore, we anticipate the use of these back-action effects to prepare ultracold and quantum states of mechanical structures, which would not be accessible with existing technology.     

Investigation of silicon on insulator fabricated by two-step O+ implantation

In this paper, we investigated the dose window of forming a continuous buried oxide (BOX) layer by single implantation at the implantation energy of 200 keV. Then, an improved two-step implantation process with second implantation dose of 3×10¹⁵ cm^?2 was developed to fabricate high quality separation by implanted oxygen (SIMOX) silicon on insulator (SOI) wafers. Compared with traditional single implantation, the implantation dose is reduced by 18.2%. In addition, the thickness and uniformity of the BOX layers were evaluated by spectroscopic ellipsometry. Defect-free top Si as well as atomic-scale sharp top Si/buried oxide interfaces were observed by transmission electron microscopy, indicating a high crystal quality and a perfect structure of the SOI fabricated by two step implantation. The top Si/BOX interface morphology of the SOI wafers fabricated by single or two-step implantation was also investigated by atomic force microscopy.     

A novel lambda negative-resistance transistor in the 0.5 μm standard CMOS process

A novel negative-resistance transistor (NRT) with a Lambda shaped I-V characteristic is demonstrated in the 0.5 μm standard CMOS process. To save on the number of component devices, this device does not use standard device models provided by CMOS processes, but changes a MOSFET and a BJT into a single device by fabricating them in the same n-well, with a p-type base layer as the MOSFET’s substrate. The NRT has a low valley current of -6.82 nA and a very high peak-to-valley current ratio of 3591. The peak current of the device is -24.49 μA which is low enough to reduce the power consumption of the deivce, and the average value of its negative resistance is about 32 kΩ. Unlike most negative-resistance devices which have been fabricated on compound semiconductor substrates in recent years, this novel NRT is based on a silicon substrate, compatible with mainstream CMOS technology. Our NRT dramatically reduces the number of devices, minimizing the area of the chip, has a low power consumption and thus a further reduction in cost.     

钢基底上预镀中间层沉积金刚石膜

利用表面预镀中间层在４５号钢上化学气相沉积（ＣＶＤ）得到了金刚石膜。钢基底表面金刚石涂层具有许多潜在应用价值，但直接在钢上沉积生长金刚石面临长的形核期，铁原子的触媒作用和热膨胀不匹配等严重问题。文中采用钢基底表面预镀中间层的方法，阻止碳向基底中扩散，增强膜基结合和抑制ＳＰ２杂化碳的沉积。分别研究了直接在钢基底上、表面预镀铜膜和表面预镀硅膜钢基底上热丝法沉积金刚石膜的工艺特点。通过ＳＥＭ、Ｒａｍａｎ谱和划痕法检验表明，钢基底表面预镀硅膜作为中间层，是一种在钢上沉积金刚石膜的有效方法。     

氧气流量对于磁过滤阴极真空弧法制备ZrO2薄膜特性的影响

ZrO₂薄膜具有高硬度、高耐磨性等优良特性，在诸多领域具有广泛的应用前景．高品质ZrO₂薄膜的制备一直是科学家们研究的一个重点和热点问题．本文利用磁过滤阴极真空弧（FCVA）技术，以金属Zr为阴极，在单晶硅（100）衬底上制备高品质ZrO₂薄膜，利用X射线衍射（XRD）、原子力显微镜（AFM）、X射线电子能谱（XPS）和纳米力学探针对薄膜的结构、形貌、成分及其性能进行表征，研究了O₂流量对于ZrO₂薄膜的晶体结构、形貌、成分以及力学性能的影响规律，获得了结晶品质良好、表面平滑且硬度较高的ZrO₂薄膜．