Growth of nanowire superlattice structures for nanoscale photonics and electronics

The assembly of semiconductor nanowires and carbon nanotubes into nanoscale devices and circuits could enable diverse applications in nanoelectronics and photonics. Individual semiconducting nanowires have already been configured as field-effect transistors, photodetectors and bio/chemical sensors. More sophisticated light-emitting diodes (LEDs) and complementary and diode logic devices have been realized using both n- and p-type semiconducting nanowires or nanotubes. The n- and p-type materials have been incorporated in these latter devices either by crossing p- and n-type nanowires or by lithographically defining distinct p- and n-type regions in nanotubes, although both strategies limit device complexity. In the planar semiconductor industry, intricate n- and p-type and more generally compositionally modulated (that is, superlattice) structures are used to enable versatile electronic and photonic functions. Here we demonstrate the synthesis of semiconductor nanowire superlattices from group III-V and group IV materials. (The superlattices are created within the nanowires by repeated modulation of the vapour-phase semiconductor reactants during growth of the wires.) Compositionally modulated superlattices consisting of 2 to 21 layers of GaAs and GaP have been prepared. Furthermore, n-Si/p-Si and n-InP/p-InP modulation doped nanowires have been synthesized. Single-nanowire photoluminescence, electrical transport and electroluminescence measurements show the unique photonic and electronic properties of these nanowire superlattices, and suggest potential applications ranging from nano-barcodes to polarized nanoscale LEDs.     

Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures

Substantial effort has been placed on developing semiconducting carbon nanotubes and nanowires as building blocks for electronic devices--such as field-effect transistors--that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems. Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes. Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 microOmega cm and remarkably high failure-current densities, >10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.     

Programmable nanowire circuits for nanoprocessors

A nanoprocessor constructed from intrinsically nanometre-scale building blocks is an essential component for controlling memory, nanosensors and other functions proposed for nanosystems assembled from the bottom up. Important steps towards this goal over the past fifteen years include the realization of simple logic gates with individually assembled semiconductor nanowires and carbon nanotubes, but with only 16 devices or fewer and a single function for each circuit. Recently, logic circuits also have been demonstrated that use two or three elements of a one-dimensional memristor array, although such passive devices without gain are difficult to cascade. These circuits fall short of the requirements for a scalable, multifunctional nanoprocessor owing to challenges in materials, assembly and architecture on the nanoscale. Here we describe the design, fabrication and use of programmable and scalable logic tiles for nanoprocessors that surmount these hurdles. The tiles were built from programmable, non-volatile nanowire transistor arrays. Ge/Si core/shell nanowires coupled to designed dielectric shells yielded single-nanowire, non-volatile field-effect transistors (FETs) with uniform, programmable threshold voltages and the capability to drive cascaded elements. We developed an architecture to integrate the programmable nanowire FETs and define a logic tile consisting of two interconnected arrays with 496 functional configurable FET nodes in an area of ～960 μm(2). The logic tile was programmed and operated first as a full adder with a maximal voltage gain of ten and input-output voltage matching. Then we showed that the same logic tile can be reprogrammed and used to demonstrate full-subtractor, multiplexer, demultiplexer and clocked D-latch functions. These results represent a significant advance in the complexity and functionality of nanoelectronic circuits built from the bottom up with a tiled architecture that could be cascaded to realize fully integrated nanoprocessors with computing, memory and addressing capabilities.     

A III-V nanowire channel on silicon for high-performance vertical transistors

Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years' time. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III-V materials, specifically InGaAs, are being explored as alternative fast channels on silicon because of their high electron mobility and high-quality interface with gate dielectrics. The idea of surrounding-gate transistors, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core-multishell nanowires as channels. Surrounding-gate transistors using core-multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.     

Epitaxial core-shell and core-multishell nanowire heterostructures

Semiconductor heterostructures with modulated composition and/or doping enable passivation of interfaces and the generation of devices with diverse functions. In this regard, the control of interfaces in nanoscale building blocks with high surface area will be increasingly important in the assembly of electronic and photonic devices. Core-shell heterostructures formed by the growth of crystalline overlayers on nanocrystals offer enhanced emission efficiency, important for various applications. Axial heterostructures have also been formed by a one-dimensional modulation of nanowire composition and doping. However, modulation of the radial composition and doping in nanowire structures has received much less attention than planar and nanocrystal systems. Here we synthesize silicon and germanium core-shell and multishell nanowire heterostructures using a chemical vapour deposition method applicable to a variety of nanoscale materials. Our investigations of the growth of boron-doped silicon shells on intrinsic silicon and silicon-silicon oxide core-shell nanowires indicate that homoepitaxy can be achieved at relatively low temperatures on clean silicon. We also demonstrate the possibility of heteroepitaxial growth of crystalline germanium-silicon and silicon-germanium core-shell structures, in which band-offsets drive hole injection into either germanium core or shell regions. Our synthesis of core-multishell structures, including a high-performance coaxially gated field-effect transistor, indicates the general potential of radial heterostructure growth for the development of nanowire-based devices.     

Ge/Si nanowire heterostructures as high-performance field-effect transistors

Semiconducting carbon nanotubes and nanowires are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs) owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes and Ge/Si core/shell nanowires. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-kappa dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures and enhanced gate coupling with high-kappa dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS microm(-1)) and on-current (2.1 mA microm(-1)) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, tau = CV/I, which represents a key metric for device applications, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.     

面向SWCNT-FET制造的介电泳装配技术

针对单壁碳纳米管(SWCNT)场效应晶体管(FET)制造过程中面临的SWCNT装配问题,采用介电泳技术实现SWCNT在微电极上的有效装配.对SWCNT在非均匀电场中所受到的介电泳力进行了相关理论分析,利用COMSOL多物理场耦合软件模拟了介电泳驱动电场,并做了大量装配实验,获得了高效装配SWCNT所需的实验参数.AFM扫描观测及电特性测试验证了这种方法的有效性,同时也为其他一维纳米材料纳电子器件的装配制造提供了借鉴.     

Ballistic carbon nanotube field-effect transistors

A common feature of the single-walled carbon-nanotube field-effect transistors fabricated to date has been the presence of a Schottky barrier at the nanotube--metal junctions. These energy barriers severely limit transistor conductance in the 'ON' state, and reduce the current delivery capability--a key determinant of device performance. Here we show that contacting semiconducting single-walled nanotubes by palladium, a noble metal with high work function and good wetting interactions with nanotubes, greatly reduces or eliminates the barriers for transport through the valence band of nanotubes. In situ modification of the electrode work function by hydrogen is carried out to shed light on the nature of the contacts. With Pd contacts, the 'ON' states of semiconducting nanotubes can behave like ohmically contacted ballistic metallic tubes, exhibiting room-temperature conductance near the ballistic transport limit of 4e(2)/h (refs 4-6), high current-carrying capability (approximately 25 micro A per tube), and Fabry-Perot interferences at low temperatures. Under high voltage operation, the current saturation appears to be set by backscattering of the charge carriers by optical phonons. High-performance ballistic nanotube field-effect transistors with zero or slightly negative Schottky barriers are thus realized.     

Persistent sourcing of coherent spins for multifunctional semiconductor spintronics.

Recent studies of n-type semiconductors have demonstrated spin-coherent transport over macroscopic distances, with spin-coherence times exceeding 100 ns; such materials are therefore potentially useful building blocks for spin-polarized electronics ('spintronics'). Spin injection into a semiconductor (a necessary step for spin electronics) has proved difficult; the only successful approach involves classical injection of spins from magnetic semiconductors. Other work has shown that optical excitation can provide a short (<500 ps) non-equilibrium burst of coherent spin transfer across a GaAs/ZnSe interface, but less than 10% of the total spin crosses into the ZnSe layer, leaving long-lived spins trapped in the GaAs layer (ref. 9). Here we report a 'persistent' spin-conduction mode in biased semiconductor heterostructures, in which the sourcing of coherent spin transfer lasts at least 1-2 orders of magnitude longer than in unbiased structures. We use time-resolved Kerr spectroscopy to distinguish several parallel channels of interlayer spin-coherent injection. The relative increase in spin-coherent injection is up to 500% in the biased structures, and up to 4,000% when p-n junctions are used to impose a built-in bias. These experiments reveal promising opportunities for multifunctional spin electronic devices (such as spin transistors that combine memory and logic functions), in which the amplitude and phase of the net spin current are controlled by either electrical or magnetic fields.     

Selection of peptides with semiconductor binding specificity for directed nanocrystal assembly

In biological systems, organic molecules exert a remarkable level of control over the nucleation and mineral phase of inorganic materials such as calcium carbonate and silica, and over the assembly of crystallites and other nanoscale building blocks into complex structures required for biological function. This ability to direct the assembly of nanoscale components into controlled and sophisticated structures has motivated intense efforts to develop assembly methods that mimic or exploit the recognition capabilities and interactions found in biological systems. Of particular value would be methods that could be applied to materials with interesting electronic or optical properties, but natural evolution has not selected for interactions between biomolecules and such materials. However, peptides with limited selectivity for binding to metal surfaces and metal oxide surfaces have been successfully selected. Here we extend this approach and show that combinatorial phage-display libraries can be used to evolve peptides that bind to a range of semiconductor surfaces with high specificity, depending on the crystallographic orientation and composition of the structurally similar materials we have used. As electronic devices contain structurally related materials in close proximity, such peptides may find use for the controlled placement and assembly of a variety of practically important materials, thus broadening the scope for 'bottom-up' fabrication approaches.     

Synthesis, assembly and applications of semiconductor nanomembranes

Research in electronic nanomaterials, historically dominated by studies of nanocrystals/fullerenes and nanowires/nanotubes, now incorporates a growing focus on sheets with nanoscale thicknesses, referred to as nanomembranes. Such materials have practical appeal because their two-dimensional geometries facilitate integration into devices, with realistic pathways to manufacturing. Recent advances in synthesis provide access to nanomembranes with extraordinary properties in a variety of configurations, some of which exploit quantum and other size-dependent effects. This progress, together with emerging methods for deterministic assembly, leads to compelling opportunities for research, from basic studies of two-dimensional physics to the development of applications of heterogeneous electronics.     

基于可控Cd掺杂In2O3纳米线的电学特性研究

文章利用化学气相沉积法合成了不同摩尔比的Cd掺杂的In2O3纳米线,制备了基于单根In2O3纳米线的底栅场效应晶体管,并研究了其电输运特性。结果表明,相对未掺杂的In2O3纳米线,In2O3∶Cd纳米线的电导率有1～2个数量级变化,载流子迁移率高达58.1cm2/(V.s),载流子浓度高达3.7×1018 cm-3。可控Cd掺杂In2O3纳米线将在纳米光电子器件方面有着广泛的应用前景。     

Room-temperature ferromagnetic nanotubes controlled by electron or hole doping

Nanotubes and nanowires with both elemental (carbon or silicon) and multi-element compositions (such as compound semiconductors or oxides), and exhibiting electronic properties ranging from metallic to semiconducting, are being extensively investigated for use in device structures designed to control electron charge. However, another important degree of freedom--electron spin, the control of which underlies the operation of 'spintronic' devices--has been much less explored. This is probably due to the relative paucity of nanometre-scale ferromagnetic building blocks (in which electron spins are naturally aligned) from which spin-polarized electrons can be injected. Here we describe nanotubes of vanadium oxide (VO(x)), formed by controllable self-assembly, that are ferromagnetic at room temperature. The as-formed nanotubes are transformed from spin-frustrated semiconductors to ferromagnets by doping with either electrons or holes, potentially offering a route to spin control in nanotube-based heterostructures.     

Low-voltage organic transistors with an amorphous molecular gate dielectric

Organic thin film transistors (TFTs) are of interest for a variety of large-area electronic applications, such as displays, sensors and electronic barcodes. One of the key problems with existing organic TFTs is their large operating voltage, which often exceeds 20 V. This is due to poor capacitive coupling through relatively thick gate dielectric layers: these dielectrics are usually either inorganic oxides or nitrides, or insulating polymers, and are often thicker than 100 nm to minimize gate leakage currents. Here we demonstrate a manufacturing process for TFTs with a 2.5-nm-thick molecular self-assembled monolayer (SAM) gate dielectric and a high-mobility organic semiconductor (pentacene). These TFTs operate with supply voltages of less than 2 V, yet have gate currents that are lower than those of advanced silicon field-effect transistors with SiO2 dielectrics. These results should therefore increase the prospects of using organic TFTs in low-power applications (such as portable devices). Moreover, molecular SAMs may even be of interest for advanced silicon transistors where the continued reduction in dielectric thickness leads to ever greater gate leakage and power dissipation.     

Dielectrophoretic assembly of carbon nanotubes and stability analysis

Nanoscale dimensions and remarkable properties of carbon nanotubes make them promising building blocks for nanoelectronics.One requirement is the need to manipulate single or multiple carbon nanotubes to bridge electronic conductors.In this paper,multi-walled carbon nanotubes with a variety of sizes are assembled onto electrodes using alternative current electric felds by dielectrophoresis.The effect of the dielectrophoretic parameters and the nanotube size as well as the length uniformity on the assembly is experimentally investigated.Current–voltage characteristics of assembled carbon nanotubes are measured.The experimental results showed that both the dielectrophoretic parameters and length uniformity of carbon nanotubes have an infuence on the stability of assembly results.Choosing uniform carbon nanotubes with an appropriate length and suffcient stiffness,which are more controllable by dielectrophoresis,is necessary for an assembly of a small number of carbon nanotubes.     

Nanotube electronics: large-scale assembly of carbon nanotubes

Nanoscale electronic devices made from carbon nanotubes, such as transistors and sensors, are much smaller and more versatile than those that rely on conventional microelectronic chips, but their development for mass production has been thwarted by difficulties in aligning and integrating the millions of nanotubes required. Inspired by biomolecular self-assembly processes, we have created chemically functionalized patterns on a surface, to which pre-grown nanotubes in solution can align themselves in huge numbers. This method allows wafer-scale fabrication of millions of carbon-nanotube circuits with single-nanotube precision, and may enable nanotube-based devices, such as computer chips and high-density sensor arrays, to be produced industrially.     

Coulomb blockade and the Kondo effect in single-atom transistors

Using molecules as electronic components is a powerful new direction in the science and technology of nanometre-scale systems. Experiments to date have examined a multitude of molecules conducting in parallel, or, in some cases, transport through single molecules. The latter includes molecules probed in a two-terminal geometry using mechanically controlled break junctions or scanning probes as well as three-terminal single-molecule transistors made from carbon nanotubes, C(60) molecules, and conjugated molecules diluted in a less-conducting molecular layer. The ultimate limit would be a device where electrons hop on to, and off from, a single atom between two contacts. Here we describe transistors incorporating a transition-metal complex designed so that electron transport occurs through well-defined charge states of a single atom. We examine two related molecules containing a Co ion bonded to polypyridyl ligands, attached to insulating tethers of different lengths. Changing the length of the insulating tether alters the coupling of the ion to the electrodes, enabling the fabrication of devices that exhibit either single-electron phenomena, such as Coulomb blockade, or the Kondo effect.     

Single-crystal gallium nitride nanotubes

Since the discovery of carbon nanotubes in 1991 (ref. 1), there have been significant research efforts to synthesize nanometre-scale tubular forms of various solids. The formation of tubular nanostructure generally requires a layered or anisotropic crystal structure. There are reports of nanotubes made from silica, alumina, silicon and metals that do not have a layered crystal structure; they are synthesized by using carbon nanotubes and porous membranes as templates, or by thin-film rolling. These nanotubes, however, are either amorphous, polycrystalline or exist only in ultrahigh vacuum. The growth of single-crystal semiconductor hollow nanotubes would be advantageous in potential nanoscale electronics, optoelectronics and biochemical-sensing applications. Here we report an 'epitaxial casting' approach for the synthesis of single-crystal GaN nanotubes with inner diameters of 30-200 nm and wall thicknesses of 5-50 nm. Hexagonal ZnO nanowires were used as templates for the epitaxial overgrowth of thin GaN layers in a chemical vapour deposition system. The ZnO nanowire templates were subsequently removed by thermal reduction and evaporation, resulting in ordered arrays of GaN nanotubes on the substrates. This templating process should be applicable to many other semiconductor systems.     

Patterning organic single-crystal transistor arrays

Field-effect transistors made of organic single crystals are ideal for studying the charge transport characteristics of organic semiconductor materials. Their outstanding device performance, relative to that of transistors made of organic thin films, makes them also attractive candidates for electronic applications such as active matrix displays and sensor arrays. These applications require minimal cross-talk between neighbouring devices. In the case of thin film systems, simple patterning of the active semiconductor layer minimizes cross-talk. But when using organic single crystals, the only approach currently available for creating arrays of separate devices is manual selection and placing of individual crystals-a process prohibitive for producing devices at high density and with reasonable throughput. In contrast, inorganic crystals have been grown in extended arrays, and efficient and large-area fabrication of silicon crystalline islands with high mobilities for electronic applications has been reported. Here we describe a method for effectively fabricating large arrays of single crystals of a wide range of organic semiconductor materials directly onto transistor source-drain electrodes. We find that film domains of octadecyltriethoxysilane microcontact-printed onto either clean Si/SiO(2) surfaces or flexible plastic provide control over the nucleation of vapour-grown organic single crystals. This allows us to fabricate large arrays of high-performance organic single-crystal field-effect transistors with mobilities as high as 2.4 cm(2) V(-1) s(-1) and on/off ratios greater than 10(7), and devices on flexible substrates that retain their performance after significant bending. These results suggest that our fabrication approach constitutes a promising step that might ultimately allow us to utilize high-performance organic single-crystal field-effect transistors for large-area electronics applications.     

Nanoscale holographic interferometry for strain measurements in electronic devices

Strained silicon is now an integral feature of the latest generation of transistors and electronic devices because of the associated enhancement in carrier mobility. Strain is also expected to have an important role in future devices based on nanowires and in optoelectronic components. Different strategies have been used to engineer strain in devices, leading to complex strain distributions in two and three dimensions. Developing methods of strain measurement at the nanoscale has therefore been an important objective in recent years but has proved elusive in practice: none of the existing techniques combines the necessary spatial resolution, precision and field of view. For example, Raman spectroscopy or X-ray diffraction techniques can map strain at the micrometre scale, whereas transmission electron microscopy allows strain measurement at the nanometre scale but only over small sample areas. Here we present a technique capable of bridging this gap and measuring strain to high precision, with nanometre spatial resolution and for micrometre fields of view. Our method combines the advantages of moiré techniques with the flexibility of off-axis electron holography and is also applicable to relatively thick samples, thus reducing the influence of thin-film relaxation effects.