Ge/Si nanowire heterostructures as high-performance field-effect transistors

Semiconducting carbon nanotubes and nanowires are potential alternatives to planar metal-oxide-semiconductor field-effect transistors (MOSFETs) owing, for example, to their unique electronic structure and reduced carrier scattering caused by one-dimensional quantum confinement effects. Studies have demonstrated long carrier mean free paths at room temperature in both carbon nanotubes and Ge/Si core/shell nanowires. In the case of carbon nanotube FETs, devices have been fabricated that work close to the ballistic limit. Applications of high-performance carbon nanotube FETs have been hindered, however, by difficulties in producing uniform semiconducting nanotubes, a factor not limiting nanowires, which have been prepared with reproducible electronic properties in high yield as required for large-scale integrated systems. Yet whether nanowire field-effect transistors (NWFETs) can indeed outperform their planar counterparts is still unclear. Here we report studies on Ge/Si core/shell nanowire heterostructures configured as FETs using high-kappa dielectrics in a top-gate geometry. The clean one-dimensional hole-gas in the Ge/Si nanowire heterostructures and enhanced gate coupling with high-kappa dielectrics give high-performance FETs values of the scaled transconductance (3.3 mS microm(-1)) and on-current (2.1 mA microm(-1)) that are three to four times greater than state-of-the-art MOSFETs and are the highest obtained on NWFETs. Furthermore, comparison of the intrinsic switching delay, tau = CV/I, which represents a key metric for device applications, shows that the performance of Ge/Si NWFETs is comparable to similar length carbon nanotube FETs and substantially exceeds the length-dependent scaling of planar silicon MOSFETs.     

Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures

Substantial effort has been placed on developing semiconducting carbon nanotubes and nanowires as building blocks for electronic devices--such as field-effect transistors--that could replace conventional silicon transistors in hybrid electronics or lead to stand-alone nanosystems. Attaching electric contacts to individual devices is a first step towards integration, and this step has been addressed using lithographically defined metal electrodes. Yet, these metal contacts define a size scale that is much larger than the nanometre-scale building blocks, thus limiting many potential advantages. Here we report an integrated contact and interconnection solution that overcomes this size constraint through selective transformation of silicon nanowires into metallic nickel silicide (NiSi) nanowires. Electrical measurements show that the single crystal nickel silicide nanowires have ideal resistivities of about 10 microOmega cm and remarkably high failure-current densities, >10(8) A cm(-2). In addition, we demonstrate the fabrication of nickel silicide/silicon (NiSi/Si) nanowire heterostructures with atomically sharp metal-semiconductor interfaces. We produce field-effect transistors based on those heterostructures in which the source-drain contacts are defined by the metallic NiSi nanowire regions. Our approach is fully compatible with conventional planar silicon electronics and extendable to the 10-nm scale using a crossed-nanowire architecture.     

ZnS和C60纳米线阵列的构筑和表征

以多孔氧化铝为模板,通过水热反应制备出ZnS 和 C₆₀纳米线阵列,分别用透射电子显微镜(TEM)、扫描电子显微镜(SEM)、X射线衍射(XRD)、拉曼光谱以及选区电子衍射图谱(SAED)等,对纳米线阵列形貌和化学成分进行表征.结果表明,ZnS 和C₆₀纳米线均为有序阵列.ZnS纳米线为多晶结构,在波长332 nm紫外光激发下, 发射519 nm特征荧光.同时介绍了水热条件下,在多孔氧化铝模板中填充目的产物,以及制备纳米线有序阵列的相关过程.该方法具有一定的普适性.     

金催化合成硫化锌纳米线及其发光性质的研究

采用金催化和直接蒸发ZnS粉末的方法,合成出大量具有纤锌矿结构的单晶ZnS纳米线。该纳米线的线径均匀,线形规则,直径在80~120 nm,长度约几十微米。研究发现纳米线的形貌对合成的温度很敏感,合成温度的升高会导致纳米线直径的迅速增加。单根纳米线EDS分析表明,ZnS纳米线线体中均匀分布着Au元素,Au元素的掺入是纳米线生长形成后由端部颗粒通过固态扩散进入纳米线中。室温光致发光谱显示:ZnS纳米线有两个发光峰,分别位于446 nm和520 nm处。446 nm的发光峰是由缺陷所致,而520 nm左右的发光峰是由Au元素掺杂所致。     

The influence of the surface migration of gold on the growth of silicon nanowires

Interest in nanowires continues to grow, fuelled in part by applications in nanotechnology. The ability to engineer nanowire properties makes them especially promising in nanoelectronics. Most silicon nanowires are grown using the vapour-liquid-solid (VLS) mechanism, in which the nanowire grows from a gold/silicon catalyst droplet during silicon chemical vapour deposition. Despite over 40 years of study, many aspects of VLS growth are not well understood. For example, in the conventional picture the catalyst droplet does not change during growth, and the nanowire sidewalls consist of clean silicon facets. Here we demonstrate that these assumptions are false for silicon nanowires grown on Si(111) under conditions where all of the experimental parameters (surface structure, gas cleanliness, and background contaminants) are carefully controlled. We show that gold diffusion during growth determines the length, shape, and sidewall properties of the nanowires. Gold from the catalyst droplets wets the nanowire sidewalls, eventually consuming the droplets and terminating VLS growth. Gold diffusion from the smaller droplets to the larger ones (Ostwald ripening) leads to nanowire diameters that change during growth. These results show that the silicon nanowire growth is fundamentally limited by gold diffusion: smooth, arbitrarily long nanowires cannot be grown without eliminating gold migration.     

Synthesis of ordered Si nanowire arrays in porous anodic aluminum oxide templates

Highly ordered polycrystalline Si nanowire arrays were synthesized in porous anodic aluminum oxide (AAO) templates by the chemical vapor deposition (CVD) method. The morphological structure, the crystal character of Si nanowire arrays and the individual nanowire were analyzed by the transmission electron microscopy (TEM), scanning electron microscopy (SEM), atom force microscopy (AFM) and the X-ray diffraction spectrum (XRD), respectively. It is shown that most fabricated silicon nanowires (SiNWs) tend to be assembled parallelly in bundles and constructed with highly orientated arrays. This method provides a simple and low cost fabricating craftwork and the diameters and lengths of SiNWs can be controlled, the large area Si nanowire arrays can be achieved easily under such a way. The curling and twisting SiNWs are fewer than those by other synthesis methods.     

Epitaxial core-shell and core-multishell nanowire heterostructures

Semiconductor heterostructures with modulated composition and/or doping enable passivation of interfaces and the generation of devices with diverse functions. In this regard, the control of interfaces in nanoscale building blocks with high surface area will be increasingly important in the assembly of electronic and photonic devices. Core-shell heterostructures formed by the growth of crystalline overlayers on nanocrystals offer enhanced emission efficiency, important for various applications. Axial heterostructures have also been formed by a one-dimensional modulation of nanowire composition and doping. However, modulation of the radial composition and doping in nanowire structures has received much less attention than planar and nanocrystal systems. Here we synthesize silicon and germanium core-shell and multishell nanowire heterostructures using a chemical vapour deposition method applicable to a variety of nanoscale materials. Our investigations of the growth of boron-doped silicon shells on intrinsic silicon and silicon-silicon oxide core-shell nanowires indicate that homoepitaxy can be achieved at relatively low temperatures on clean silicon. We also demonstrate the possibility of heteroepitaxial growth of crystalline germanium-silicon and silicon-germanium core-shell structures, in which band-offsets drive hole injection into either germanium core or shell regions. Our synthesis of core-multishell structures, including a high-performance coaxially gated field-effect transistor, indicates the general potential of radial heterostructure growth for the development of nanowire-based devices.     

Novel Approach to the Design of Optoelectronic Heterostructures Based on Indium and Copper Sulfides

1 Results Heterostructures,based on ternary CuInS(Se2) chalcogenides and related binary compounds (Cu2-xCh,CuCh,In2Ch3 and InCh; Ch=S,Se) are considered appear to be a matter of choice for producing promising optoelectronic devices.In the present work we propose and consider a very simple way for the formation of sulfide and selenide heterostructures.The main idea is assumes a novel two-stage method of synthesis and nonstoichiometry control for heterostructures of InxS(Se)1-x/Si,CuInS(Se)2/Si and InxS1-...     

Si NWs/GQDs复合结构的设计及其光电催化性能

采用金属催化化学蚀刻法制备硅纳米线阵列（silicon nanowire arrays,Si NWs）,通过高速旋涂仪将自上而下法制备的石墨烯量子点（graphene quantum dots, GQDs）负载到Si NWs上。X射线光电子能谱（X-ray photoelectron spectroscopy, XPS）等表征结果证明,GQDs能够通过高速旋涂仪负载到Si NWs上。扫描电子显微镜（scanning electron microscopy, SEM）形貌观测结果表明,蚀刻时间与Si NWs纳米线长度成正比。光电化学测试结果表明,性能最优的蚀刻时间为45 min。与原始硅片相比,GQDs负载的Si NWs光电密度达到了0.95 mA/cm²,性能提升了30多倍。电化学交流阻抗（electrochemical impedance spectroscopy, EIS）测试结果表明：GQDs的加入能显著提升载流子的传输效率。紫外–可见漫反射光谱（ultravioletray-visible diffuse reflectance spectroscopy, UV-Vis DRS）结果显示负载GQDs可以有效提升Si NWs对光的吸收效果。     

Enhanced thermoelectric performance of rough silicon nanowires

Approximately 90 per cent of the world's power is generated by heat engines that use fossil fuel combustion as a heat source and typically operate at 30-40 per cent efficiency, such that roughly 15 terawatts of heat is lost to the environment. Thermoelectric modules could potentially convert part of this low-grade waste heat to electricity. Their efficiency depends on the thermoelectric figure of merit ZT of their material components, which is a function of the Seebeck coefficient, electrical resistivity, thermal conductivity and absolute temperature. Over the past five decades it has been challenging to increase ZT > 1, since the parameters of ZT are generally interdependent. While nanostructured thermoelectric materials can increase ZT > 1 (refs 2-4), the materials (Bi, Te, Pb, Sb, and Ag) and processes used are not often easy to scale to practically useful dimensions. Here we report the electrochemical synthesis of large-area, wafer-scale arrays of rough Si nanowires that are 20-300 nm in diameter. These nanowires have Seebeck coefficient and electrical resistivity values that are the same as doped bulk Si, but those with diameters of about 50 nm exhibit 100-fold reduction in thermal conductivity, yielding ZT = 0.6 at room temperature. For such nanowires, the lattice contribution to thermal conductivity approaches the amorphous limit for Si, which cannot be explained by current theories. Although bulk Si is a poor thermoelectric material, by greatly reducing thermal conductivity without much affecting the Seebeck coefficient and electrical resistivity, Si nanowire arrays show promise as high-performance, scalable thermoelectric materials.     

TeO2纳米线的制备及其室温NO2气敏特性

以金属Te颗粒为原料,采用热蒸发法于镀金硅基板表面制备出TeO2纳米线,并以其为气敏材料制备成气敏元件.采用XRD,SEM和TEM表征TeO2纳米线的相组成和微观结构,结果表明,TeO2纳米线具有单一的四方相晶体结构,长度约为几十微米,直径约为80~600nm.在TeO2纳米线的顶端未发现Au颗粒,表明TeO2纳米线按照气-固机制进行生长.气敏特性的研究结果表明,TeO2纳米线呈现p型半导体特性,在室温条件下对NO2气体具有良好的响应,气体灵敏度与NO2气体体积分数呈线性增加关系.最后对气敏机制进行了初步探讨.     

Si纳米线的Au催化固-液-固生长与结构表征

为:Au膜层厚度为5～10 nm,温度为1 100 ℃,N2气流量为1.5 L/min.     

电沉积Ni纳米线阵列及其磁学性能研究

为了解决因受阳极氧化铝(AAO)孔道直径限制导致合成的金属纳米线尺寸单一、磁性受限的问题,采用二次阳极氧化法制备了不同孔径的阳极氧化铝(AAO)模板,依据模板辅助电沉积法,在不同孔径AAO模板内生长了Ni纳米线阵列,利用SEM,TEM,XRD和EDS等技术对制备的Ni纳米线阵列形貌、微观结构和成分进行表征,通过物理性能...     

SnO2纳米线的制备及结构表征

以SnO₂粉末和碳粉的混合物为源,高纯氮气为载气,利用化学气相沉积法在1 000 ℃下,在溅有Au的单晶Si衬底上制备了SnO₂纳米线。用SEM、XRD测试技术对样品进行了结构、形貌的表征,利用PL技术分析了样品的发光特性。由分析可知,样品均为四方金红石结构,退火时间对样品形貌具有一定的影响,但不影响其结构。所制备的SnO₂纳米线结晶质量较高,其生长遵循VLS机制。     

稀土掺杂TiO2纳米线阵列的可见光催化性能

采用溶胶-电泳沉积法在多孔阳极氧化铝模板上制备了TiO2光催化纳米线,合成了具有高比表面积的糖葫芦状M/TiO2(M代表La3+、Ce3+、Nd3+)纳米线阵列体系。采用SEM对样品进行了表征,表明M/TiO2纳米线阵列保持了模板的有序性;对甲基橙的可见光降解实验表明,稀土金属离子掺杂TiO2纳米线阵列体系具有非常优良的可见光催化性能;紫外-可见吸收光谱测试表明,La3+、Ce3+、Nd3+掺杂增强了TiO2在可见光区域的吸收能力,吸收带边红移至可见光区,未掺杂的TiO2禁带宽度为3.24eV,掺La3+、Ce3+、Nd3+的M/TiO2禁带宽度分别减小至2.6eV、2.8eV、2.0eV,这和光催化性能是大致相对应的。     

Au纳米耦合结构表面等离激元的EELS分析

应用透射电子显微镜中电子能量损失谱仪(TEM-EELS),对电子束激发的单晶Au纳米线耦合结构及单晶/多晶纳米薄膜的表面等离激元(SPs)特征进行分析.结果表明:直径约为10 nm的两单晶Au纳米线平行耦合时,单根纳米线和耦合结构中均存在位于2.4 eV 的SPs共振,耦合结构中SPs的纵模数增加;单晶及多晶Au纳米薄膜在1.4 eV附近存在SPs模式,相较于单晶薄膜,多晶Au纳米薄膜的SPs共振峰位出现明显红移.     

钛纳米线力学、热学和电子性质的结构与尺寸依赖性

为了研究金属纳米物理性质与结构和尺寸之间的关系,我们选择不同结构和生长序列的几个典型的超细Ti纳米线,即四边形、五边形和六边形序列,以及六边形序列的两个较大体系,以分别考察结构和尺寸效应.我们计算了Ti纳米线的角关联函数和振动谱,电子态密度用平面波赝势的密度泛函电子结构自洽场计算.采用分子动力学方法研究Ti纳米线的热力学融化行为.结果表明,Ti纳米线的振动性质和电子性质表现出渐进的尺寸演化和明显的结构关联;较小的纳米线的电子态密度是类似分子的离散谱,而当线的直径大于1*!nm时便表现为类似体材料的电子结构.Ti纳米线的融化行为既不同于团簇也不同样块体材料,表现出明显的结构和尺寸依赖性.对较大尺寸的纳米线,我们观察到从螺旋多壳的圆柱体到类似块体的结构相变.     

SnO2纳米线阵列的制备及纳米器件的制作

采用简单的溶胶-凝胶方法在多孔阳极氧化铝模板(AAM)的微孔中制备了高度有序的SnO2纳米线阵列。XRD,SEM和TEM对样品进行了结构和形貌的表征,结果表明,高度有序的SnO2纳米线具有四方相的多晶结构,纳米线连续均匀;并对SnO2纳米线阵列的生长机理进行了探讨;最后用聚焦离子束沉积设备制作了单根SnO2纳米线器件。     

磁性氧化铁纳米线的制备与表征

通过溶胶-凝胶法在氧化铝模板（AAO）中制备出了磁性Fe_2O_3纳米线阵列,然后去除AAO模板得到磁性Fe_2O_3纳米线。用SEM,TEM,FTIR,EDX,VSM对磁性纳米线的形貌、微结构和磁性能进行表征。SEM和TEM结果显示磁性纳米线的直径约为50～80nm,长度在8～10μm,长径比为120～180;FTIR和EDX结果表明制备的产物是磁性Fe_2O_3纳米线;VSM结果表明磁性氧化铁纳米线阵列存在明显的磁各向异性。此外,采用Zeta电位仪对磁性Fe_2O_3纳米线表面的电性进行了研究,结果表明纳米线表面带正电荷,有利于和动物细胞相结合。     

电化学组装一维纳米线阵列温差电材料

低维温差电材料具有比块状温差电材料更高的优值,因而研制具有纳米线阵列结构的温差电材料对于提高材料的温差电转换效率具有重要意义.以具有纳米孔阵列结构的氧化铝多孔模板为阴极,在含有Bi 3、HTeO2 1的酸性溶液中,采用直流电沉积技术,通过在氧化铝多孔模板的纳米级微孔中沉积铋和碲,实现了一维纳米线阵列铋碲温差电材料的电化学组装.环境扫描电子显微镜(ESEM)和透射电子显微镜(TEM)的分折表明,电化学组装出的铋碲纳米线分布均匀,形状规则.铋碲纳米线的组成可方便地通过调整电沉积电位加以控制.